Design Verification

Apple; Cupertino (CA); On-site; USD 174,000 - 225,000; Full time

Job summary

APPLE INC is seeking a senior verification engineer in Cupertino to design and architect verification environments for IPs and SoCs. You will work with design, architecture and software teams to understand use cases, corner conditions and drive robust test cases.

This role emphasizes scalable verification and test bench development. The candidate will apply SystemVerilog/UVM, run RTL simulations with VCS/Xcelium/ModelSim, and use JasperGold for formal checks.

Qualifications

• Master's degree in Electrical Engineering or Computer Engineering with 3 years of related verification experience.
• SystemVerilog and UVM methodology to implement scalable verification environments and test cases.
• RTL/gate-level simulations using VCS, Xcelium or ModelSim.
• Formal verification with JasperGold for connectivity and coverage.
• Coverage tools such as Mentor InFact or Cadence vManager/IMC for code and functional coverage.
• C/C++ functional and performance modeling for verification.
• Computer architecture and digital design knowledge for failure analysis and debugging.
• Waveform debugging with Indago and Verdi; scripting in Perl, Tcl, Python.
• Version control with Perforce, Git and ClearCase.

Responsibilities

• Design and architect verification environments; develop test plans and test benches.
• Collaborate with design, micro-architecture, and software teams to cover use cases and corner conditions.
• Drive test case creation, regression planning, and coverage closure to guarantee IP/SoC quality.
• Communicate results and debug complex functional/performance issues across teams.
• Support design verification lifecycle from planning to final sign-off.

Skills

SystemVerilog

UVM

RTL/Simulation

C/C++

JasperGold

Mentor InFact

Cadence vManager

Perforce

Git

Python

Indago

Verdi

Perl

Tcl

ClearCase

Education

Master's degree in Electrical or Computer Engineering

Tools

VCS

Xcelium

ModelSim

JasperGold

Mentor InFact

Cadence vManager

Indago

Verdi

Git

Perforce

ClearCase

Job description

Summary

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Design and architect specifications and work closely with design & micro-architecture teams. Understand the functional & performance goals of the design. Develop test plans, tests & coverage plans as well as define our next generation verification methodology & test benches. Communicate and collaborate with design, architecture and software teams to understand the use cases and corner conditions and drive test cases. Ensure the quality of the SoC, IP, and/or subsystem by working on one or more types of IP such as Neural Engine hardware, DRAM subsystems, memory controller logic, Encode and Decode systems for ProRes and other codec formats (such as VP9 and AV1), hardware security including cryptographic algorithm implementations), high-speed IO standards (such as PCI Express, DisplayPort, MIPI), power management and fabric infrastructure, memory cache management, and display subsystems for variety of panels and products. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $174,149 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location. PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

Master’s degree or foreign equivalent in Electrical Engineering or Computer Engineering or related field and 3 years of experience in the job offered or related occupation. 3 years of experience with each of the following skills is required: Utilising SystemVerilog and UVM methodology to implement scalable and reusable verification environment and test cases to verify designs. Utilizing VCS, xcelium or modelSim tools to run RTL, gate, and power aware simulations. Utilizing formal verification tools (JasperGold) for connectivity, assertion based functional and unreachability formal analysis. Utilizing coverage tools (Mentor InFact, Cadence vManager/IMC) for code and functional coverage analysis and closure. Applying C and/or C++ functional and performance models in verification. Applying knowledge in computer architecture and digital design in failure analysis and hardware debug. Utilising waveform debug tools (Indago and Verdi) to triage and debug functional and performance issues. Developing and conducting test plans and test attributes based on design specifications. Experience in scripting languages PERL, tcl, and python for aiding verification. Using version control tools Perforce, Git, and Clearcase for source code control.

Preferred Qualifications

N/A