Design Verification Engineer – OVM Expert (Full-Chip)

Redolent Infotech Pvt. Ltd.; Austin (TX); On-site; USD 120,000 - 155,000; Full time

Job summary

Redolent Infotech Pvt. Ltd. in Austin, TX is seeking a Design Verification Engineer (Strong OVM) on a contract basis. Location is Austin, TX, with a 6 to 12+ month engagement and DOE compensation. The role demands expertise in OVM, UVM, and SystemVerilog test benches for full-chip verification.

You will work with simulation tools such as VCS, Cadence IES, and related environments to validate ASIC/SoC designs, including memory interfaces and PCIe verification.

Qualifications

• Must have strong OVM experience for full-chip verification.
• Experience with UVM, VMM and SystemVerilog.
• Proficiency in Verilog/SystemVerilog test benches and simulation environments.

Responsibilities

• Develop and verify full-chip testbenches using OVM/UVM.
• Perform verification across AXI/NoC/PCIe domains as needed.
• Utilize formal property checking and gate-level simulation tools when required.

Job description

Redolent Infotech Pvt. Ltd. in Austin, TX is seeking a Design Verification Engineer (Strong OVM) on a contract basis. Location is Austin, TX, with a 6 to 12+ month engagement and DOE compensation. The role demands expertise in OVM, UVM, and SystemVerilog test benches for full-chip verification.

You will work with simulation tools such as VCS, Cadence IES, and related environments to validate ASIC/SoC designs, including memory interfaces and PCIe verification.