Senior Design Verification Engineer

ASICSoft; United States; Remote; USD 120,000 - 160,000; Full time

Job summary

A technology company is seeking a highly skilled Senior Design Verification Engineer to lead IOMMU verification for complex SoC projects. Candidates should have 7-10 years of verification experience, strong expertise in SystemVerilog and UVM, and excellent problem-solving skills. This is a remote contract position lasting 6-12 months.

Qualifications

• 7-10+ years of experience in ASIC/SoC design verification.
• Expert-level proficiency in SystemVerilog and UVM.
• Solid understanding of IOMMU architecture and virtualization.

Responsibilities

• Lead and execute verification of IOMMU designs.
• Develop and maintain SystemVerilog/UVM-based testbenches.
• Collaborate with design engineers and track bugs.

Skills

SystemVerilog

UVM

IOMMU verification

Problem-solving skills

Attention to detail

Communication skills

Tools

VCS

Questa

Xcelium

Job description

Location: Remote

Duration: 6–12 Months (Contract)

Overview

We are seeking a highly skilled Senior Design Verification Engineer with strong expertise in IOMMU (Input–Output Memory Management Unit) verification. This role will involve working on complex SoC projects, leveraging your deep understanding of memory management, virtualization, and peripheral interactions. The ideal candidate will have proven experience in SystemVerilog, UVM, and industry-standard verification methodologies to ensure robust and high-quality design validation.

Key Responsibilities

• Lead and execute the verification of IOMMU designs, ensuring compliance with functional and performance requirements.
• Develop, implement, and maintain SystemVerilog/UVM-based testbenches for block-level and SoC-level verification.
• Create and review verification plans, test scenarios, coverage models, and verification metrics.
• Collaborate closely with design engineers, architects, and other verification team members to identify issues and drive resolution.
• Analyze waveforms, debug simulation failures, and track bugs through to closure.
• Drive coverage closure for functional, code, and assertion-based coverage metrics.
• Contribute to process improvements, verification methodology enhancements, and best practices documentation.

Required Qualifications

• 7-10+ years of experience in ASIC/SoC design verification, with strong hands-on expertise in IOMMU verification.
• Expert-level proficiency in SystemVerilog and UVM.
• Solid understanding of IOMMU architecture, address translation, TLB management, interrupt handling, and virtualization support.
• Strong experience in constrained-random verification, functional coverage, and regression management.
• Proficiency with simulation tools such as VCS, Questa, or Xcelium.
• Familiarity with protocols such as PCIe, AXI, and other high-speed interconnects.
• Excellent problem-solving skills, attention to detail, and ability to work independently in a remote environment.
• Strong verbal and written communication skills.

Preferred Qualifications

• Experience with formal verification techniques.
• Exposure to performance verification and emulation platforms.
• Familiarity with scripting languages such as Python, Perl, or Tcl for automation.