Design Verification Engineer (strong OVM)

Redolent Infotech Pvt. Ltd.; Austin (TX); On-site; USD 120,000 - 155,000; Full time

Job summary

Redolent Infotech Pvt. Ltd. in Austin, TX is seeking a Design Verification Engineer (Strong OVM) on a contract basis. Location is Austin, TX, with a 6 to 12+ month engagement and DOE compensation. The role demands expertise in OVM, UVM, and SystemVerilog test benches for full-chip verification.

You will work with simulation tools such as VCS, Cadence IES, and related environments to validate ASIC/SoC designs, including memory interfaces and PCIe verification.

Qualifications

• Must have strong OVM experience for full-chip verification.
• Experience with UVM, VMM and SystemVerilog.
• Proficiency in Verilog/SystemVerilog test benches and simulation environments.

Responsibilities

• Develop and verify full-chip testbenches using OVM/UVM.
• Perform verification across AXI/NoC/PCIe domains as needed.
• Utilize formal property checking and gate-level simulation tools when required.

Job description

• Austin, TX

We have the following urgent requirement with ourclient:

Design Verification Engineer ( Strong OVM)

Location: Austin, TX

Duration: 6 to 12+ Months

Compensation: DOE

Requirements

• Strong OVM experience is must for this role

Details

• Requires strong experience with development of Strong OVM ( must ), UVM, VMM and/or Verilog, SystemVerilog test benches for full chip testbench and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test full chip FPGA fabric and SoCs.
• Requires strong understanding of state of the art of verification techniques, including assertion and metric-driven verification.
• Verification experience AXI, NoC, HBM, DDR4, PCIe verification is a plus.
• Verification experience in full chip verification is a plus.
• Strong understanding of different phases of ASIC and/or full custom chip development is required.
• Experience in modeling SystemC and using SystemC based models in verification is a plus.
• Experience with FPGA programming and software is a plus.
• Verification experience in PCIe, Processors, Graphics is a plus.
• Experience with formal property checking tools such as Cadence (IEV), Jasper, and Synopsys (Magellan) is a plus.
• Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.
• Some DFX/DFT and UPF/power-aware-simulation experience is a plus