Design Verification Engineer: High-Performance IP & NoCs

Etched; Austin (TX); On-site; USD 120,000 - 160,000; Full time

Benefits offered by this job

Medical, dental, and vision packages

$500 per month credit for waiving medical benefits

Housing subsidy of $2k per month

Relocation support

Daily lunch + dinner in office

Job summary

A leading technology company in Austin is looking for a Design Verification Engineer to enhance custom IPs for cutting-edge technologies. This position requires expertise in UVM and SystemVerilog, strong debugging skills, and collaboration with engineers on design functionality. Candidates should have experience in verifying digital designs and will enjoy benefits including comprehensive medical coverage and housing assistance. Expect some travel to the San Jose office for collaboration.

Qualifications

• Proficiency with UVM and SystemVerilog is essential.
• Ability to debug complex digital designs.
• Solid knowledge of computer architecture fundamentals.

Responsibilities

• Develop and maintain UVM/SystemVerilog testbenches.
• Define and execute verification plans for functional correctness.
• Work closely with architects and designers on validation.

Skills

Proficiency with UVM

SystemVerilog

Strong debugging skills

Knowledge of computer architecture

Tools

Python

Perl

TCL

Job description

A leading technology company in Austin is looking for a Design Verification Engineer to enhance custom IPs for cutting-edge technologies. This position requires expertise in UVM and SystemVerilog, strong debugging skills, and collaboration with engineers on design functionality. Candidates should have experience in verifying digital designs and will enjoy benefits including comprehensive medical coverage and housing assistance. Expect some travel to the San Jose office for collaboration.