Senior Interface IP Verification Engineer

Etched; Austin (TX); Hybrid; USD 120,000 - 160,000; Full time

Benefits offered by this job

Medical, dental, and vision packages

Housing subsidy

Relocation support

Wellness benefits

Daily meals

Job summary

A cutting-edge technology company in Austin is seeking a Design Verification Engineer to join their Interface IP DV team. The role involves collaborating with architects and vendors to ensure IP correctness and performance. Candidates should have over 5 years of design verification experience, alongside expertise in UVM/SystemVerilog and industry-standard IP interfaces. This position offers competitive benefits including housing subsidies and relocation support. Interactions with the team in San Jose are expected during certain months.

Qualifications

• 5+ years of design verification experience required.
• Hands-on experience with UVM/SystemVerilog methodologies.
• Ability to understand standard IP interfaces and protocols.

Responsibilities

• End to end ownership of one or more IP subsystems.
• Develop and maintain UVM/SystemVerilog-based verification environments.
• Drive coverage closure and sign-off by defining metrics.

Skills

Design verification experience

UVM/SystemVerilog

Understanding of PCIe and Ethernet

Collaborative communication

Tools

Testbenches

Job description

A cutting-edge technology company in Austin is seeking a Design Verification Engineer to join their Interface IP DV team. The role involves collaborating with architects and vendors to ensure IP correctness and performance. Candidates should have over 5 years of design verification experience, alongside expertise in UVM/SystemVerilog and industry-standard IP interfaces. This position offers competitive benefits including housing subsidies and relocation support. Interactions with the team in San Jose are expected during certain months.