Etched.ai, Inc. is seeking a Design Verification Engineer in Austin to ensure custom IPs are robust and silicon-ready. The role includes collaborating with architects on performance verification, tuning software for bottlenecks, and developing tests in SystemVerilog and Python. Ideal candidates should have a strong understanding of ASIC design and digital systems. Benefits include comprehensive health coverage and meals at the office. Expect collaboration in San Jose for ramp-up and ongoing teamwork.
Qualifications
Strong understanding of digital design, RTL, and ASIC design flows.
Hands-on experience with performance verification, simulation, and modeling.
Comfortable developing checkers, coverage monitors, and testbenches in SystemVerilog.
Skilled in writing Python scripts for automation and data analysis.
Responsibilities
Work closely with architects and RTL designers on verifying design performance.
Identify performance bottlenecks with software developers.
Develop test plans and verification tools.
Debug performance issues on silicon.
Skills
Digital design understanding
Performance verification experience
SystemVerilog development
Python scripting
Chip subsystem performance modeling
Memory hierarchies knowledge
Performance bottleneck analysis
Kernel level performance metrics
Tools
SystemVerilog
Python
Job description
Etched.ai, Inc. is seeking a Design Verification Engineer in Austin to ensure custom IPs are robust and silicon-ready. The role includes collaborating with architects on performance verification, tuning software for bottlenecks, and developing tests in SystemVerilog and Python. Ideal candidates should have a strong understanding of ASIC design and digital systems. Benefits include comprehensive health coverage and meals at the office. Expect collaboration in San Jose for ramp-up and ongoing teamwork.