Design Verification Engineer — High-Perf IPs & NoCs

Etched.ai, Inc.; San Jose (CA); On-site; USD 100,000 - 150,000; Full time

Benefits offered by this job

Medical, dental, and vision packages

$500 monthly credit for waiving medical benefits

Housing subsidy of $2k per month

Relocation support

Wellness benefits

Daily lunch + dinner in office

Job summary

Etched.ai, Inc. is seeking a Design Verification Engineer for their Internal IP DV team in San Jose. This role involves ensuring custom IPs are robust and silicon-ready, developing and maintaining UVM/SystemVerilog testbenches, and collaborating with architects and designers. Candidates should have proficiency with UVM, SystemVerilog, and strong debugging skills. Benefits include medical coverage, a housing subsidy, and daily meals in the office.

Qualifications

• Proficiency with UVM and SystemVerilog.
• Strong debugging and problem‑solving skills for complex digital designs.
• Hands‑on experience verifying datapaths, memory systems, interconnects, or high‑throughput fabrics.

Responsibilities

• Develop and maintain UVM/SystemVerilog testbenches for high-performance IPs.
• Define and execute verification plans covering functional correctness and performance.
• Debug complex datapath and protocol issues in RTL and testbench environments.

Skills

UVM

SystemVerilog

Debugging skills

Problem-solving skills

Knowledge of computer architecture

Tools

Python

Perl

TCL

Job description

Etched.ai, Inc. is seeking a Design Verification Engineer for their Internal IP DV team in San Jose. This role involves ensuring custom IPs are robust and silicon-ready, developing and maintaining UVM/SystemVerilog testbenches, and collaborating with architects and designers. Candidates should have proficiency with UVM, SystemVerilog, and strong debugging skills. Benefits include medical coverage, a housing subsidy, and daily meals in the office.