Design Verification Engineer - Hardware for AI Accelerators

River AI Inc.; Palo Alto, Austin (CA, TX); On-site; USD 200,000 - 420,000; Full time

Benefits offered by this job

Health benefits

Unlimited PTO

Relocation support

Job summary

River AI Inc. is seeking exception design verification engineers to ensure our high-performance custom silicon is functionally correct.

Starting from architectural definitions, you will define test benches and verification environments across simulation, formal, and emulation methods, collaborating with RTL, performance modeling, and compiler teams. You will build scalable UVM environments, develop constrained-random tests, implement coverage models, use formal methods where applicable, and

Qualifications

• Bachelor's degree in Electrical Engineering or Computer Engineering or Computer Science, and 5+ years industry experience.
• Deep, hands-on experience building UVM-based environments (Agents, Scoreboards, Drivers, Monitors, and Predictors).
• Expert command of SystemVerilog for verification, including OOP principles, randomization, and functional coverage.
• Strong understanding of computer architecture, including pipelines, cache coherency protocols, memory consistency models, and high-speed interconnects (e.g., AXI, CHI).
• Proven track record of verifying high-performance silicon (CPU, GPU, AI accelerator, or complex SoC).
• A highly collaborative mindset and a bias for action to push boundaries and co-design effectively with other engineers.

Responsibilities

• Define comprehensive verification plans by extracting features from architectural and micro-architectural specifications for complex blocks.
• Architect and implement scalable, reusable, and robust test benches using SystemVerilog and UVM (Universal Verification Methodology).
• Develop complex sequences and test cases to achieve high functional coverage, ensuring the design handles corner cases and error conditions.
• Define and implement functional coverage models and perform detailed code coverage analysis.
• Leverage formal methods (SVA, Property Checking) where applicable to exhaustively prove correctness of critical logic.
• Use emulation and prototyping platforms like ZeBu/HAPS and Palladium/Protium for scaled testing.
• Debug failures using waveform viewers and work with RTL designers to resolve issues.
• Build and maintain regression flows and productivity tools using Python, Perl, Bash, or TCL to streamline verification.

Skills

UVM-based environments

SystemVerilog verification

Computer architecture

Silicon verification

Collaborative mindset

Education

Bachelor's degree in Electrical/Computer Engineering or CS

Tools

Jasper

VC Formal

Job description

River AI Inc. is seeking exception design verification engineers to ensure our high-performance custom silicon is functionally correct.

Starting from architectural definitions, you will define test benches and verification environments across simulation, formal, and emulation methods, collaborating with RTL, performance modeling, and compiler teams. You will build scalable UVM environments, develop constrained-random tests, implement coverage models, use formal methods where applicable, and