Design Verification Engineer, Hardware

River AI; Palo Alto (CA); On-site; USD 200,000 - 420,000; Full time

Benefits offered by this job

Health benefits? (see listing)

Job summary

River AI is seeking exception design verification engineers to ensure our high-performance custom silicon is functionally correct. Based in Austin, TX or Palo Alto, CA, you will define test benches and verification environments across simulation, formal, and emulation, collaborating with RTL, performance modeling, and compiler teams.

You will develop scalable UVM test benches, constrained-random sequences, and coverage models, while debugging issues to accelerate silicon bring-up and

Qualifications

• Bachelor’s degree in Electrical Engineering or Computer Engineering or Computer Science, and 5+ years industry experience.
• Deep, hands-on experience building UVM-based environments (Agents, Scoreboards, Drivers, Monitors, and Predictors).
• Expert command of SystemVerilog for verification, including OOP principles, randomization, and functional coverage.
• Strong understanding of computer architecture, including pipelines, cache coherency protocols, memory consistency models, and high-speed interconnects (e.g., AXI, CHI).
• Proven track record of verifying high-performance silicon (CPU, GPU, AI accelerator, or complex SoC).
• A highly collaborative mindset and a bias for action to push boundaries and co-design effectively with other engineers.

Responsibilities

• Verification Strategy & Planning: Define comprehensive verification plans by extracting features from architectural and micro-architectural specifications for complex blocks.
• UVM Environment Development: Architect and implement scalable, reusable, and robust test benches using SystemVerilog and UVM (Universal Verification Methodology).
• Constrained-Random Testing: Develop complex sequences and test cases to achieve high functional coverage, ensuring the design handles architectural corner cases and error conditions.
• Coverage-Driven Verification: Define and implement functional coverage models and perform detailed code coverage analysis to quantify verification progress.
• Formal Verification: Leverage formal methods (SVA, Property Checking) where applicable to exhaustively prove the correctness of critical logic.
• Emulation: Use emulation and prototyping platforms like ZeBu/HAPS and Palladium/Protium to perform scaled testing.
• Debug & Analysis: Debug failures using waveform viewers and work closely with RTL designers to resolve functional bugs and architectural non-compliance.
• Automation & Scripting: Build and maintain regression flows and productivity tools using Python, Perl, Bash, or TCL to streamline the verification cycle.

Skills

UVM-based environments

SystemVerilog

Computer architecture

Silicon verification

Team collaboration

Education

Bachelor's degree in Electrical/Computer Engineering or CS

Tools

Jasper Formal

VC Formal

ZeBu

Palladium

Protium

Python

Perl

Bash

TCL

Job description

At River AI, our mission is to create personal AI owned and shaped by each individual. To achieve this, we are rewriting the entire stack from scratch: personal hardware for local inference, bespoke training infrastructure, next-generation UIs, and frontier deep learning research.

Who we are

We are scientists, engineers, and builders from the industry's top tech companies and AI labs. We bring a proven track record of scaling consumer systems for hundreds of millions of users and architecting the pre-training infrastructure behind today's frontier models.

About The Role

We are seeking exception design verification engineers to ensure our high-performance custom silicon is functionally correct. Starting from architectural and micro-architectural definitions, you will define test bench boundaries and implement test environments across a variety of verification methodologies (simulation, formal, emulation, etc). You will collaborate with RTL design, performance modeling and verification, and compiler teams.

What You’ll Do

• Verification Strategy & Planning: Define comprehensive verification plans by extracting features from architectural and micro-architectural specifications for complex blocks.
• UVM Environment Development: Architect and implement scalable, reusable, and robust test benches using SystemVerilog and UVM (Universal Verification Methodology).
• Constrained-Random Testing: Develop complex sequences and test cases to achieve high functional coverage, ensuring the design handles architectural corner cases and error conditions.
• Coverage-Driven Verification: Define and implement functional coverage models and perform detailed code coverage analysis to quantify verification progress.
• Formal Verification: Leverage formal methods (SVA, Property Checking) where applicable to exhaustively prove the correctness of critical logic.
• Emulation: Use emulation and prototyping platforms like ZeBu/HAPS and Palladium/Protium to perform scaled testing.
• Debug & Analysis: Debug failures using waveform viewers and work closely with RTL designers to resolve functional bugs and architectural non-compliance.
• Automation & Scripting: Build and maintain regression flows and productivity tools using Python, Perl, Bash, or TCL to streamline the verification cycle.

Skills and Qualification

Minimum Qualifications

• Bachelor’s degree in Electrical Engineering or Computer Engineering or Computer Science, and 5+ years industry experience.
• Deep, hands-on experience building UVM-based environments (Agents, Scoreboards, Drivers, Monitors, and Predictors).
• Expert command of SystemVerilog for verification, including OOP principles, randomization, and functional coverage.
• Strong understanding of computer architecture, including pipelines, cache coherency protocols, memory consistency models, and high-speed interconnects (e.g., AXI, CHI).
• Proven track record of verifying high-performance silicon (CPU, GPU, AI accelerator, or complex SoC).
• A highly collaborative mindset and a bias for action to push boundaries and co-design effectively with other engineers.

Preferred Qualifications: (We encourage you to apply even if you don’t meet all of these)

• Proficiency SystemVerilog Assertions (SVA) and formal tools (Jasper, VC Formal) to catch temporal logic bugs at the source.
• Understanding of emulation and prototyping solutions and test environments.
• Hands-on experience in post-Silicon bringup, testing, and debug.
• Experience in workflow management, CI/CD, regression definition and visibility, EDA tool configuration and usage, and other infrastructure tasks.

Logistics & Benefits

• Location: This role is based in Austin, Texas or Palo Alto, California.
• Compensation: Depending on background, skills, and experience, the expected annual salary range for this position is $200,000 - $420,000 USD, plus equity.
• Visa Sponsorship: We sponsor visas. We can't guarantee success for every candidate or role, but if you're the right fit, we're committed to working through the visa process.
• Benefits: River AI offers generous health, dental, and vision benefits, unlimited PTO, and relocation support as needed.