Hardware Performance Engineer, AI Accelerators

River AI; Palo Alto (CA); On-site; USD 200,000 - 420,000; Full time

Benefits offered by this job

Health, dental, vision benefits

Unlimited PTO

Relocation support

Job summary

River AI is seeking exceptional hardware performance engineers to architect, model, and correlate high-performance custom silicon. You will develop simulators to predict how the AI accelerator architecture and SoC will handle real-world models, collaborating with compiler, IR, and software teams as well as RTL design engineers.

You will design and implement high-performance models in C++/SystemC, explore micro-architectural changes, and validate results against RTL/pre-silicon emulators.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science.
• 5+ years of industry experience with advanced process nodes (7nm+).
• Proficiency in C/C++ or SystemC.
• Experience with compilers (LLVM/GCC/XLA) and high-performance kernels (CUDA/Triton).
• Knowledge of computer architecture of SoCs/CPUs/GPUs/AI accelerators.
• Experience profiling hardware with performance counters and trace analysis tools.
• Collaborative mindset for cross-team co-design.

Responsibilities

• Design and implement high-performance hardware models in C++ or SystemC.
• Conduct micro-architectural exploration and evaluate architectural changes.
• Profile AI kernels and software stacks to generate representative traces.
• Collaborate with compiler and kernel teams to optimize software mapping to hardware.
• Validate performance models against RTL and pre-silicon emulators.
• Identify and quantify system-level bottlenecks.

Skills

C++/SystemC

Performance modeling

Hardware architecture

RTL/Emulation

Compiler integration

Education

Bachelor's in EE/CE/CS

Tools

QEMU models

LLVM/GCC

RTL emulators

Job description

River AI is seeking exceptional hardware performance engineers to architect, model, and correlate high-performance custom silicon. You will develop simulators to predict how the AI accelerator architecture and SoC will handle real-world models, collaborating with compiler, IR, and software teams as well as RTL design engineers.

You will design and implement high-performance models in C++/SystemC, explore micro-architectural changes, and validate results against RTL/pre-silicon emulators.