Design Verification Engineer — AI Hardware & Silicon Debug

Cerebras; Sunnyvale (CA); On-site; USD 190,000 - 230,000; Full time

Job summary

Cerebras Systems in Sunnyvale, CA is seeking a Design Verification Engineer to join our verification team and contribute to validating our AI chip architecture. You will craft and run tests, debug complex capabilities, and help ensure silicon-first quality from early verification to bring-up.

You will work with SystemVerilog testbenches, DPI and UVM, applying scripting in Python or Perl, and collaborating across RTL, physical design, firmware, and software validation to deliver scalable

Qualifications

• Excellent debugging and problem-solving skills.
• Deep knowledge of SystemVerilog testbench, DPI and UVM.
• Strong programming skills and software engineering practices (OO design).
• Experience developing scalable, portable testbenches and components.
• Experience with verification methodologies and tools (simulators, waveform viewers, build/run automation, coverage, gate-level sims).
• Proficient in Python or Perl scripting.
• Good interpersonal and collaborative skills.
• Self-motivated with strong problem-solving drive.
• 3–5+ years of Design Verification experience.

Responsibilities

• Work with architects, designers, post-silicon and software engineers to ensure a high-quality design for silicon.
• Develop and implement verification strategies, tests and coverage plans based on micro-architecture.
• Create verification methodologies and reusable environments (stimulus, checkers, assertions, coverage).
• Implement tests, manage regressions, gather coverage and debug failures.
• Collaborate with cross-functional teams including architecture, RTL, physical design, firmware and validation.
• Analyze and debug issues across simulation, emulation and silicon bring-up phases.
• Continuously enhance verification infrastructure and flows for efficiency and quality.
• Contribute to the evolution of verification methodology and best practices.

Skills

SystemVerilog

DPI

UVM

Python

Perl

Debugging

Software engineering

3–5+ years in DV

Education

BS or MS in CS or ECE

Tools

SystemVerilog

UVM

Simulators

Waveform viewers

Job description

Cerebras Systems in Sunnyvale, CA is seeking a Design Verification Engineer to join our verification team and contribute to validating our AI chip architecture. You will craft and run tests, debug complex capabilities, and help ensure silicon-first quality from early verification to bring-up.

You will work with SystemVerilog testbenches, DPI and UVM, applying scripting in Python or Perl, and collaborating across RTL, physical design, firmware, and software validation to deliver scalable