Design Verification Engineer

Acceler8 Talent; Mountain View (CA); A distancia; USD 120.000 - 210.000; Jornada completa

Descripción de la vacante

Acceler8 Talent seeks a Design Verification Engineer for AI accelerator silicon, with Mountain View or remote work options. You will translate architectural intent into verification strategies, build environments and tests, and drive coverage closure across compute, memory and connectivity subsystems.

You will develop reusable SystemVerilog/UVM environments, assertion-based checks, and use simulation/formal methods to expose corner cases.

Formación

• Proficient in SystemVerilog/UVM environments.
• Experience with assertion-based verification and formal methods.
• Strong debugging and diagnostic skills across silicon blocks and testbenches.

Responsabilidades

• Translate architectural specs into verification plans, testbenches and tests.
• Develop reusable SystemVerilog and UVM environments and checks.
• Use simulation and formal verification to analyze functional behavior and corner cases.
• Drive coverage closure, diagnose failures and contribute to sign-off decisions.
• Build portable tests/drivers for validation and post-silicon debugging.
• Collaborate with architecture, RTL and validation teams to resolve issues.
• Identify coverage goals and prioritize scenarios based on risks.
• Develop protocol checks and assertions and select methods appropriately.
• Investigate failures across testbench, model and RTL boundaries.
• Contribute to verification reviews with clear risk reporting.

Conocimientos

SystemVerilog

UVM

Formal verification

Simulation

Debugging

Coverage analysis

Programming for tests

Herramientas

Emulation

Prototyping

Descripción del empleo

Design Verification Engineer

AI accelerator silicon | Mountain View or remote

The opportunity

Acceler8 Talent is partnering with an AI compute startup building a full-stack platform for large-scale AI workloads. The team is hiring a Design Verification Engineer to help deliver dependable accelerator silicon, with ownership spanning design specifications, verification implementation and silicon milestones.

You will help turn architectural intent into a rigorous verification strategy, build the environments and tests that expose failures, and drive coverage closure. The work connects compute, memory and connectivity rather than stopping at regression execution.

Technical scope

Verification spans the relationship between compute, memory management and high-speed connectivity. You will consider how individual functions behave and how interactions create system-level failures. The team needs engineers who can build the verification artifacts themselves, reason about the strengths and limits of simulation and formal techniques, and carry issues through to closure. Portable tests and drivers should help connect pre-silicon verification with later validation and debugging.

What you will do

• Translate architectural and design specifications into verification plans, testbenches, tests and supporting models.
• Develop reusable SystemVerilog and UVM environments and assertion-based checks.
• Use simulation and formal verification to investigate functional behavior and difficult corner cases.
• Drive structural and functional coverage closure, diagnose failures and contribute to sign-off decisions.
• Build portable tests or drivers that support validation and post-silicon debugging.
• Collaborate with architecture, RTL and validation engineers to resolve issues across the silicon lifecycle.
• Identify coverage goals from architectural behavior and implementation risks, then use coverage results to find missing scenarios and prioritize further work.
• Develop checks and assertions for protocol behavior, control sequencing and corner cases, selecting simulation or formal approaches appropriate to the problem.
• Investigate failures across testbench, model and RTL boundaries, working with designers to establish reproducible cases and validate fixes.
• Contribute to verification reviews with clear reporting on remaining risks, coverage gaps and milestone readiness.

What you will bring

• Personal ownership of verification implementation and delivery for complex silicon blocks, subsystems or SoCs.
• Production experience with SystemVerilog, UVM and assertion-based verification, with comfort using formal and simulation methods.
• Strong debugging skills and the ability to connect failures to microarchitectural behavior.
• Experience closing coverage and explaining the technical evidence behind verification milestones.
• Understanding of compute, memory-management or connectivity microarchitecture and how it shapes verification choices.
• Programming or modeling skills that support test development, reference behavior, automation and failure analysis.
• Ability to justify coverage and closure decisions using technical evidence, including what has been exercised and what risks remain.
• Useful experience
• CPU, GPU, accelerator, memory-controller or complex connectivity verification with comparable ownership of implementation and closure.
• Emulation, prototyping, silicon validation or bring-up experience that connects pre-silicon tests to hardware behavior.
• Experience creating portable tests, drivers or reusable infrastructure across blocks and development stages.
• Engineers at multiple career levels are relevant; the scope and complexity of work you have owned matter more than a fixed tenure.