Design Verification Engineer (Data Fabric Verification Engineer)

iFlow Inc.; Sunnyvale (CA); On-site; USD 110,000 - 150,000; Full time

Job summary

iFlow Inc. is looking for a Design Verification Engineer located in Sunnyvale, California. This long-term position requires expertise in System Verilog and a background in designing verification environments. The ideal candidate will have at least 5 years of experience and a strong understanding of RTL design and formal verification tools.

Responsibilities include writing test sequences, coordinating with engineers for logic design verification, and ensuring verification quality metrics are met. A Bachelor's or Master's degree in Computer or Electrical Engineering is preferred.

Qualifications

• 5 to 20 years of experience in design verification.
• Architected and developed complex verification environments.
• Good understanding of clock gating and design implementation.

Responsibilities

• Write tests and testbench components in System Verilog and UVM.
• Coordinate with RTL engineers for logic design verification.
• Interact with architects and designers to develop expertise.

Skills

System Verilog

Formal verification tools

Programming (Perl, Ruby, Make)

Understanding of computer organization

Experience with RTL design

Education

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering

Tools

VCS

Cadence

Mentor Graphics

Job description

Job Title: Design Verification Engineer (Data Fabric Verification Engineer)

Location: Sunnyvale, CA & Austin, TX

Duration: Long term

Experience: 5 to 20 years

Preferred Experience

• Architected and developed complex verification environments in System Verilog, including scripting using Perl, Ruby, Make, or the likes.
• Exposure to RTL design, software development, formal verification, or other related domains.
• Good understanding of computer organization/architecture.
• Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics.

Key Responsibilities

• Write tests, sequences, and testbench components in System Verilog and UVM along with formal to achieve verification of the design.
• Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design.
• Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture.
• Collaborate with architects, hardware engineers and multiple IP development groups.
• Drive formal verification for the block and write formal properties and assertions to verify the design.
• Responsible for verification quality metrics like pass rates, code coverage and functional coverage.

Academic Credentials

Bachelors or Masters degree in computer engineering/Electrical Engineering preferred.