Data Fabric Verification Engineer | SystemVerilog & Formal

iFlow Inc.; Sunnyvale (CA); On-site; USD 110,000 - 150,000; Full time

Job summary

iFlow Inc. is looking for a Design Verification Engineer located in Sunnyvale, California. This long-term position requires expertise in System Verilog and a background in designing verification environments. The ideal candidate will have at least 5 years of experience and a strong understanding of RTL design and formal verification tools.

Responsibilities include writing test sequences, coordinating with engineers for logic design verification, and ensuring verification quality metrics are met. A Bachelor's or Master's degree in Computer or Electrical Engineering is preferred.

Qualifications

• 5 to 20 years of experience in design verification.
• Architected and developed complex verification environments.
• Good understanding of clock gating and design implementation.

Responsibilities

• Write tests and testbench components in System Verilog and UVM.
• Coordinate with RTL engineers for logic design verification.
• Interact with architects and designers to develop expertise.

Skills

System Verilog

Formal verification tools

Programming (Perl, Ruby, Make)

Understanding of computer organization

Experience with RTL design

Education

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering

Tools

VCS

Cadence

Mentor Graphics

Job description

iFlow Inc. is looking for a Design Verification Engineer located in Sunnyvale, California. This long-term position requires expertise in System Verilog and a background in designing verification environments. The ideal candidate will have at least 5 years of experience and a strong understanding of RTL design and formal verification tools.

Responsibilities include writing test sequences, coordinating with engineers for logic design verification, and ensuring verification quality metrics are met. A Bachelor's or Master's degree in Computer or Electrical Engineering is preferred.