Data Fabric Verification Engineer | SystemVerilog & Formal

iFlow Inc.

Sunnyvale (CA)

Presencial

USD 110 000 - 150 000

Tempo integral

14 dias+
Gerador de candidaturas

Recebe uma resposta deste empregador — um currículo e uma carta de apresentação adaptados exatamente ao que estão a contratar.

Ultrapassa os filtros ATS

Resumo da oferta

iFlow Inc. is looking for a Design Verification Engineer located in Sunnyvale, California. This long-term position requires expertise in System Verilog and a background in designing verification environments. The ideal candidate will have at least 5 years of experience and a strong understanding of RTL design and formal verification tools.

Responsibilities include writing test sequences, coordinating with engineers for logic design verification, and ensuring verification quality metrics are met. A Bachelor's or Master's degree in Computer or Electrical Engineering is preferred.

Qualificações

  • 5 to 20 years of experience in design verification.
  • Architected and developed complex verification environments.
  • Good understanding of clock gating and design implementation.

Responsabilidades

  • Write tests and testbench components in System Verilog and UVM.
  • Coordinate with RTL engineers for logic design verification.
  • Interact with architects and designers to develop expertise.

Conhecimentos

System Verilog
Formal verification tools
Programming (Perl, Ruby, Make)
Understanding of computer organization
Experience with RTL design

Formação académica

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering

Ferramentas

VCS
Cadence
Mentor Graphics

Descrição da oferta de emprego

iFlow Inc. is looking for a Design Verification Engineer located in Sunnyvale, California. This long-term position requires expertise in System Verilog and a background in designing verification environments. The ideal candidate will have at least 5 years of experience and a strong understanding of RTL design and formal verification tools.

Responsibilities include writing test sequences, coordinating with engineers for logic design verification, and ensuring verification quality metrics are met. A Bachelor's or Master's degree in Computer or Electrical Engineering is preferred.

Obtém a tua avaliação gratuita e confidencial do currículo.

ou arrasta e larga o ficheiro aqui.

Similar jobs

Ofertas semelhantes que vale a pena comparar

Design Verification Engineer (Data Fabric Verification Engineer)
Design Verification Engineer (Data Fabric Verification Engineer)

iFlow Inc. • Sunnyvale (CA)

Presencial
USD 110 000 - 150 000
Senior Verification Engineer: SystemVerilog/UVM for SoC
Senior Verification Engineer: SystemVerilog/UVM for SoC

iFlow Inc. • Santa Clara (CA)

Presencial
USD 120 000 - 150 000
Design Verification Engineer
Design Verification Engineer

Themesoft Inc. • Austin (TX)

Presencial
USD 120 000 - 150 000
Design Verification Engineer
Design Verification Engineer

iFlow Inc. • Santa Clara (CA)

Presencial
USD 120 000 - 150 000
Design Verification Engineer
Design Verification Engineer

Platform Recruitment • Austin (TX)

Presencial
USD 90 000 - 130 000
Data Fabric Verification Engineer
Data Fabric Verification Engineer

Wipro • Santa Clara (UT)

Presencial
USD 60 000 - 148 500
Medical and dental benefits
Disability insurance
Paid time off
+1
Associate Design Verification Engineer - UVM SystemVerilog
Associate Design Verification Engineer - UVM SystemVerilog

Millennium Software and Staffing Inc • San Jose (CA)

Presencial
USD 70 000 - 100 000
FPGA Verification Engineer | UVM/SystemVerilog Expert
FPGA Verification Engineer | UVM/SystemVerilog Expert

Allps GmbH • Santa Clara (CA)

Presencial
USD 206 309 376
Design Verification Lead - Must be local to TX,CA or MA
Design Verification Lead - Must be local to TX,CA or MA

MTK Technologies • Austin (TX)

Presencial
USD 120 000 - 150 000
Design Verification Engineers
Design Verification Engineers

Tachyum • Las Vegas (NV)

Presencial
USD 100 000 - 140 000
Competitive salary
Benefits package
Professional development
+3