Design Verification Engineer - Contractor

Verilab; United States; On-site; USD 70,000 - 110,000; Full time

Job summary

Verilab seeks an experienced verification engineer for a contract engagement supporting client projects across audio, automotive, communications, processors, space, and video. You will contribute to verification planning, create robust verification environments, and drive milestones to verification closure.

Ideal candidate has 7+ years of hands-on SystemVerilog/UVM experience, coverage-driven verification, and proven ability to translate requirements into test plans, with strong collaboration

Qualifications

• BSc/MSc in Electronic Engineering, Computer Engineering, or Computer Science.
• At least 7 years of project-proven verification experience.
• Strong SystemVerilog/UVM development experience, including: block and integration level verification, coverage driven, self-checking environments, high level sequence based stimulus, complex transaction based checkers with scoreboards, register models, protocol checks (AXI, DDRx, PCIe, USB).
• Verification planning experience: requirements capture and traceability, effort estimation and prioritization, metrics to assess progress and closure.
• Ownership of deliverables from planning through implementation and meeting deadlines with clear collaboration with clients and Verilab teams.

Responsibilities

• Develop verification environments and coverage-driven testbenches.
• Plan, implement, and drive verification closure for projects.
• Collaborate with client and Verilab teams, ensuring timely delivery and clear communication.

Skills

SystemVerilog

UVM

Verification planning

Coverage-driven verification

Testbenches

Scoreboards

AXI

PCIe

USB

Register models

Education

BSc/MSc in Electrical/Computer Engineering or CS

Tools

AXI

PCIe

USB

Job description

Description Job Summary Verilab is seeking an experienced verification engineer for a contract engagement supporting our clients with high quality verification services. Our projects span a diverse range of designs and application areas, including audio, automotive, communications, processors, space, and video. As a contractor, you will contribute your expertise to verification planning and implementation, with responsibilities defined by the scope of the engagement. You will develop robust verification environments, address complex technical challenges, and help achieve project milestones and verification closure. You will collaborate with Verilab consultants and client engineering teams, bringing technical insight, clear communication, and ownership of your deliverables. This is an opportunity to apply your experience to challenging designs while working alongside some of the most knowledgeable people in the industry.

Requirements Key Qualifications

• BSc/MSc in Electronic Engineering, Computer Engineering, or Computer Science.
• At least 7 years of project-proven verification experience.
• Strong SystemVerilog/UVM development experience, including:
• Block and integration level verification.
• Development of coverage driven, self-checking verification environments from scratch.
• High level sequence based stimulus.
• Complex transaction based checkers, including scoreboards with data translation and ordering.
• Register models.
• Specification level checks for protocols such as AXI, DDRx, PCIe, and USBx.
• Demonstrated verification planning experience, including:
• Requirements capture and traceability.
• Effort estimation and prioritization.
• Use of metrics to assess progress and determine verification closure.
• Ability to take ownership of agreed deliverables, from planning through implementation.
• Experience meeting demanding project deadlines and resolving technical challenges.
• Effective communication and collaboration with consultants, clients, and engineering teams.

Additional Requirements

• All candidates must be a US person (citizen or permanent resident).
• The ability to travel is required.