Contract Senior Verification Engineer – SystemVerilog/UVM

Verilab; United States; On-site; USD 70,000 - 110,000; Full time

Job summary

Verilab seeks an experienced verification engineer for a contract engagement supporting client projects across audio, automotive, communications, processors, space, and video. You will contribute to verification planning, create robust verification environments, and drive milestones to verification closure.

Ideal candidate has 7+ years of hands-on SystemVerilog/UVM experience, coverage-driven verification, and proven ability to translate requirements into test plans, with strong collaboration

Qualifications

• BSc/MSc in Electronic Engineering, Computer Engineering, or Computer Science.
• At least 7 years of project-proven verification experience.
• Strong SystemVerilog/UVM development experience, including: block and integration level verification, coverage driven, self-checking environments, high level sequence based stimulus, complex transaction based checkers with scoreboards, register models, protocol checks (AXI, DDRx, PCIe, USB).
• Verification planning experience: requirements capture and traceability, effort estimation and prioritization, metrics to assess progress and closure.
• Ownership of deliverables from planning through implementation and meeting deadlines with clear collaboration with clients and Verilab teams.

Responsibilities

• Develop verification environments and coverage-driven testbenches.
• Plan, implement, and drive verification closure for projects.
• Collaborate with client and Verilab teams, ensuring timely delivery and clear communication.

Skills

SystemVerilog

UVM

Verification planning

Coverage-driven verification

Testbenches

Scoreboards

AXI

PCIe

USB

Register models

Education

BSc/MSc in Electrical/Computer Engineering or CS

Tools

AXI

PCIe

USB

Job description

Verilab seeks an experienced verification engineer for a contract engagement supporting client projects across audio, automotive, communications, processors, space, and video. You will contribute to verification planning, create robust verification environments, and drive milestones to verification closure.

Ideal candidate has 7+ years of hands-on SystemVerilog/UVM experience, coverage-driven verification, and proven ability to translate requirements into test plans, with strong collaboration