Design Verification Engineer

ZipRecruiter; Mountain View (CA); On-site; USD 200,000 - 250,000; Full time

Job summary

An innovative firm is seeking a Design Verification Engineer to enhance the quality of their cutting-edge designs. In this role, you will leverage your expertise in System Verilog and UVM to build robust verification environments and develop comprehensive test plans. You will collaborate with cross-functional teams to debug and resolve issues, ensuring the highest standards of design integrity. This position offers an exciting opportunity to contribute to groundbreaking projects in a dynamic and supportive environment. If you are passionate about design verification and eager to make a significant impact, this role is perfect for you.

Qualifications

• Strong understanding of SV and UVM with good debugging skills.
• Experience in developing test plans based on functional requirements.

Responsibilities

• Build UVM/System Verilog-based verification environments for testing.
• Collaborate with teams to ensure design quality across domains.

Skills

System Verilog

UVM

Debugging Skills

AMBA Protocols

Test Plans Development

Coverage Analysis

Tools

UVM/System Verilog-based Verification Environments

Power-aware Simulations

UPF/CPF

Job description

Job Description

Hello All,

Role: Design Verification Engineer

Location: Mountain View, CA

Key Responsibilities:

• Strong understanding of SV and UVM and good debugging skills.
• Understanding of AMBA protocols.
• Understand design specs and develop test plans based on functional and architectural requirements.
• Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing.
• Develop directed and random testcases, perform coverage analysis, and close functional/code coverage.
• Debug simulation failures and work closely with RTL designers to resolve issues.
• Execute regression runs, analyze results, and contribute to continuous improvements.
• Integrate and run power-aware simulations, low power checks, and work with UPF/CPF as needed.
• Collaborate with DFT/PD/RTL teams and post-silicon validation to ensure design quality across domains.
• Document test environments, test plans, and results for internal and external reviews.

Regards,

Rajashekhar

[e-mail]