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Design Verification Engineer

LanceSoft, Inc.

San Jose (CA)

Remote

USD 200,000 - 250,000

Full time

30+ days ago

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Job summary

An innovative firm in the semiconductor industry is seeking a skilled Recruitment Specialist with expertise in ASIC verification and debugging. This role requires a deep understanding of UVM and System Verilog, as well as experience in both Linux and Windows environments. You will be instrumental in developing verification frameworks and automating workflows, contributing to cutting-edge projects in a dynamic and collaborative setting. If you are passionate about technology and looking to make an impact, this opportunity is perfect for you.

Qualifications

  • Masters + 5 years or Bachelors + 8 years preferred.
  • Proficient in Verilog, System Verilog, C, and C++.

Responsibilities

  • Developing UVM based verification frameworks and testbenches.
  • Automating workflows in a distributed compute environment.

Skills

IP level ASIC verification
Debugging firmware
RTL code simulation
UVM testbenches
Linux environment
Windows environment
Verilog
System Verilog
C
C++

Education

Masters degree
Bachelors degree

Tools

Simulation tools
UVM

Job description

This range is provided by LanceSoft, Inc. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$90.00/hr - $90.00/hr

Recruitment Specialist at LanceSoft, Inc. Semiconductor / VLSI / EDA / Embedded

Pay Rate: $85/hr to $95/hr on W2

Remote

Responsibilities
  • Ideally Masters + 5 years or Bachelors + 8 years is preferred
  • Proficient in IP level ASIC verification
  • Proficient in debugging firmware and RTL code using simulation tools
  • Proficient in using UVM testbenches and working in Linux and Windows environments
  • Experienced with Verilog, System Verilog, C, and C++
  • Developing UVM based verification frameworks and testbenches, processes and flows
  • Automating workflows in a distributed compute environment
  • Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
Seniority level

Mid-Senior level

Employment type

Contract

Job function

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