Design Verification Engineer

Intelliswift - An LTTS Company; Sunnyvale (CA); On-site; USD 220,000 - 240,000; Full time

Job summary

Join a forward-thinking company as an Assistant Manager in Technical Recruitment. In this pivotal role, you'll lead the charge in defining and implementing cutting-edge IP/SoC verification plans while collaborating with cross-functional teams to ensure the highest design quality. Your expertise in SystemVerilog and C/C++ will be crucial in driving design verification to closure. This full-time position offers a competitive salary range and comprehensive benefits, including medical and vision insurance. If you're ready to make an impact in the semiconductor industry, this opportunity is perfect for you!

Benefits

Medical insurance

401(k)

Vision insurance

Qualifications

• 7+ years of experience in SystemVerilog/UVM methodology and C/C++ based verification.
• Track record of first-pass success in ASIC development cycles.
• Experience in architecting and implementing Design Verification infrastructure.

Responsibilities

• Define and implement IP/SoC verification plans.
• Collaborate with cross-functional teams to ensure design quality.
• Drive Design Verification to closure based on defined metrics.

Skills

SystemVerilog/UVM methodology

C/C++ based verification

EDA tools

Python

TCL

Perl

Shell scripting

Design Verification

Education

Bachelor's degree in Computer Science

Equivalent practical experience

Tools

Mercurial (Hg)

Git

SV Assertions

Job description

2 weeks ago Be among the first 25 applicants

Intelliswift - An LTTS Company provided pay range

This range is provided by Intelliswift - An LTTS Company. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$220,000.00/yr - $240,000.00/yr

Direct message the job poster from Intelliswift - An LTTS Company

Assistant Manager - Technical Recruitment | Strategic Sourcing, Technical Recruiting

Full time role.

Sunnyvale, California or Austin, Texas

Note: No hybrid or remote

Job Description & Skill Requirement

Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification.

Develop functional tests based on verification test plan.

Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.

Debug, root-cause and resolve functional failures in the design, partnering with the Design team.

Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.

Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.

Minimum Qualifications

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.

7+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification.

Track record of 'first-pass success' in ASIC development cycles.

7+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies.

Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.

Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle.

Preferred Qualifications

Experience in development of UVM based verification environments from scratch.

Experience verifying GPU/CPU designs.

Experience with micro-architectural performance verification.

Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs.

Experience with verification of ARM/RISC-V based sub-systems or SoCs.

Experience with IP or integration verification of high-speed interfaces like PCIe, RoCE, DDR, HBM, Ethernet.

Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation.

Experience working across and building relationships with cross-functional design, model and emulation teams.

Experience with revision control systems like Mercurial(Hg), Git or SVN.

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Industries

  Information Technology & Services, Semiconductor Manufacturing, and Computers and Electronics Manufacturing

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Inferred from the description for this job

Medical insurance

401(k)

Vision insurance

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