Design Verification Engineer

Sintegra Inc.; San Francisco (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Sintegra Inc. in San Francisco seeks an experienced Senior Verification Engineer to drive verification for cloud and data center infrastructure across storage and computing.

You will define test plans, develop verification environments, and collaborate with design and software teams to ensure robust silicon and IPs.

Qualifications

• Experience in ASIC/FPGA verification with testbenches.
• Strong knowledge of high-speed protocols PCIe or Ethernet.
• Proficiency in SystemVerilog, Verilog and verification methods.

Responsibilities

• Collaborate with design teams to review specs, architectures and micro-architectures.
• Define comprehensive test plans and verification strategies.
• Develop block- and chip-level verification environments.
• Generate and analyze functional and code coverage metrics.
• Execute regressions, debug and triage failures in simulation.
• Validate features and partner with software teams in the lab.

Skills

SystemVerilog

Verilog

UVM

OVM

VMM

PCIe

Ethernet

Education

BSEE

MSEE

Job description

We are seeking experienced Senior Verification Engineers to join our rapidly expanding team, driving breakthrough innovations in cloud and data center infrastructure across both storage and computing.

If you are passionate about cutting-edge technology, thrive in fast-paced environments, and want to help shape the next generation of enterprise solutions, we’d love to hear from you.

Responsibilities

• Collaborate closely with design teams to review and understand specifications, architectures, and micro-architectures.
• Define comprehensive test plans and verification strategies.
• Develop block-level and chip-level verification environments.
• Generate and analyze functional and code coverage metrics.
• Execute regressions, debug, and triage failures in simulation environments.
• Validate features and partner with software teams to debug issues in the lab.

Requirements

• BSEE with 7+ years or MSEE with 5+ years of relevant experience.
• Advanced knowledge of ASIC/FPGA verification flows, including simulation, testbench development, and post-silicon validation.
• Proven experience with industry-standard high-speed protocols PCI Express (PCIe), or Ethernet is a must.
• Strong expertise in SystemVerilog and Verilog.
• Hands-on experience developing testbenches using UVM, OVM, or VMM methodologies.