Design Verification Engineer – VLSI / Semiconductor

nexacode; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Nexacode is seeking an experienced Design Verification Engineer to support semiconductor opportunities, focusing on VLSI/ASIC/SoC verification and testbench development.

You will build and maintain verification environments using SystemVerilog and UVM, develop testbenches, and ensure comprehensive functional coverage across complex SoCs.

Qualifications

• Strong experience in VLSI / ASIC / SoC verification.
• Proficiency in SystemVerilog.
• Hands-on UVM experience.
• Strong understanding of RTL and digital design.
• Experience with simulation, debugging, and regression.
• Knowledge of functional/code coverage.
• Bachelor's or Master's degree in EE, ECE, Computer Engineering, or related field.

Responsibilities

• Develop and execute verification plans for ASIC, SoC, and semiconductor designs.
• Build and maintain verification environments using SystemVerilog and UVM.
• Develop testbenches, test cases, and functional coverage.
• Analyze simulation results and debug design issues.
• Support regression testing and verification closure.
• Collaborate with RTL designers, architects, and other engineering teams.

Skills

VLSI / ASIC / SoC verification

SystemVerilog

UVM

RTL & digital design

Simulation & debugging

Regression testing

Functional/code coverage

Education

Bachelor's / Master's in EE, ECE, Computer Engineering

Job description

Location: San Jose, CA

Job Type: Full-Time

About Nexacode

Nexacode is a Software and Technology company delivering engineering, software development, technology solutions, and specialized technical talent through its dedicated Recruitment Division.

Role Overview

We are looking for experienced Design Verification Engineers with strong VLSI/ASIC/SoC verification experience to support current and upcoming semiconductor engineering opportunities.

Key Responsibilities

• Develop and execute verification plans for ASIC, SoC, and semiconductor designs.
• Build and maintain verification environments using SystemVerilog and UVM.
• Develop testbenches, test cases, and functional coverage.
• Analyze simulation results and debug design issues.
• Support regression testing and verification closure.
• Collaborate with RTL designers, architects, and other engineering teams.

Required Skills

• Strong experience in VLSI / ASIC / SoC verification
• Proficiency in SystemVerilog
• Hands-on UVM experience
• Strong understanding of RTL and digital design
• Experience with simulation, debugging, and regression
• Knowledge of functional/code coverage
• Bachelor's or Master's degree in EE, ECE, Computer Engineering, or related field

Preferred

• Experience with chipset / semiconductor products
• VCS, Xcelium, or Questa
• Python, Perl, or Tcl scripting
• Experience with complex SoCs, IPs, or high-speed interfaces