Design Infrastructure Engineer for HBM & EDA Automation

Micron Technology; Nebraska; On-site; USD 120,000 - 150,000; Full time

Job summary

Micron Technology's Heterogeneous Integration Group is seeking a Design Infrastructure Engineer to build and scale characterization infrastructure across multiple HBM-related designs, spanning internal nodes and external foundries like TSMC. You will develop scalable flows for standard and custom cell characterization, impacting timing closure and model accuracy.

Collaborating with design teams, you will enable robust Liberty model generation, MCMM characterization, and silicon validation

Qualifications

• Bachelor's or Master's in Electrical Engineering with strong CMOS fundamentals.
• Experience with standard or custom cell characterization, Liberty modeling and SPICE-based sims.
• Proficient in Python, Perl, or Tcl for automation and STA tooling.
• Experience with SiliconSmart or PrimeLib required.

Responsibilities

• Develop scalable infrastructure for standard and custom cell characterization, including timing, power, noise, and SI modeling.
• Create automated flows for MCMM characterization and Liberty model generation, validation, and regression.
• Characterize across multiple process technologies, including internal nodes and external foundries like TSMC.
• Define requirements for TSV interfaces, PHY paths, and high-speed datapath elements with design teams.
• Integrate characterization into broader design/verification ecosystems and improve data quality.
• Lead debug and continuous improvement by root-causing mismatches between SPICE, extracted views, STA, and silicon.

Skills

CMOS design

Liberty modeling

SPICE simulations

Scripting (Python/Perl/Tcl)

STA flows

SiliconSmart

PrimeLib

Education

Bachelors or Masters in Electrical Engineering

Tools

SiliconSmart

PrimeLib

Job description

Micron Technology's Heterogeneous Integration Group is seeking a Design Infrastructure Engineer to build and scale characterization infrastructure across multiple HBM-related designs, spanning internal nodes and external foundries like TSMC. You will develop scalable flows for standard and custom cell characterization, impacting timing closure and model accuracy.

Collaborating with design teams, you will enable robust Liberty model generation, MCMM characterization, and silicon validation