Senior Foundry Interface Engineer for HBM & AI Enablement

Micron Technology, Inc; Folsom (CA); On-site; USD 150,000 - 308,000; Full time

Job summary

Micron Technology, Inc. is seeking a Principal Foundry Interface Design Engineer in the United States to bridge design teams, foundries, and development groups for scalable, high‑performance HBM architectures.

You will contribute to technology alignment, circuit simulation, test‑chip validation, PDK enablement, and AI‑driven productivity initiatives, shaping the DTCO and long‑term HBM roadmap.

Qualifications

• BS, MS, or PhD or equivalent experience in Electrical Engineering, Computer Engineering, or related field.
• 6+ years of semiconductor industry experience and solid understanding of advanced semiconductor technology development.
• Strong grasp of advanced CMOS technology nodes, FinFET devices, and process integration.
• Hands-on experience with: HSPICE simulations, Device characterization, Standard cell benchmarking, PPA analysis, Parasitic extraction and physical verification.
• Experience in driving AI-enabled engineering practices and automation to improve the efficiency of DTCO analysis, foundry collateral evaluation, PDK enablement, benchmarking, and collaboration across build teams.

Responsibilities

• Act as the primary technical interface between foundry partners and Micron design organizations.
• Drive closure of design-process gaps through collaborative engagement with foundry process teams.
• Influence foundry roadmaps related to TSV, BEOL, reliability, and design enablement.
• Define technology requirements for future HBM and custom memory products.
• Perform HSPICE simulations for technology evaluation and design optimization.

Skills

HSPICE simulations

Device characterization

Parasitic extraction

PPA analysis

Beol/TSV knowledge

AI-enabled automation

Education

BS/MS/PhD in Electrical or Computer Engineering

Job description

Micron Technology, Inc. is seeking a Principal Foundry Interface Design Engineer in the United States to bridge design teams, foundries, and development groups for scalable, high‑performance HBM architectures.

You will contribute to technology alignment, circuit simulation, test‑chip validation, PDK enablement, and AI‑driven productivity initiatives, shaping the DTCO and long‑term HBM roadmap.