Characterization Engineer – Standard & Custom Cells

Micron Technology, Inc

Richardson (TX)

On-site

USD 120,000 - 160,000

Full time

14 days+

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Benefits offered by this job

Medical, dental and vision plans
Paid time off
Paid holidays

Job summary

Micron Technology, Inc. in Richardson, TX is seeking a Design Engineer to build scalable characterization infrastructure for standard and custom cells across multiple process nodes, including TSV and HBM related dies.

You will develop automated flows, generate and validate Liberty models, and collaborate with design teams to meet timing, power, and reliability targets for next-gen memory architectures.

Qualifications

  • BS/MS in Electrical Engineering or related field with strong CMOS fundamentals.
  • Experience with standard or custom cell characterization and Liberty modeling.
  • Experience with SPICE-based simulation and STA flows.

Responsibilities

  • Develop scalable infrastructure for standard and custom cell characterization.
  • Create reusable flows for multi-corner, multi-mode characterization across PVT spaces.
  • Build and validate Liberty models; ensure regression readiness.
  • Support characterization across multiple process technologies (including foundries).
  • Collaborate with design teams on TSV interfaces and high-speed datapaths.

Skills

CMOS digital and mixed-signal design
PVT variation understanding
Liberty/CCS modeling
SPICE-based simulation
STA and timing libraries
Python/Perl/Tcl scripting
EDA infrastructure and automation

Education

Bachelor's or Master's Degree in Electrical Engineering

Tools

SiliconSmart
PrimeLib
SPICE simulators

Job description

Micron Technology, Inc. in Richardson, TX is seeking a Design Engineer to build scalable characterization infrastructure for standard and custom cells across multiple process nodes, including TSV and HBM related dies.

You will develop automated flows, generate and validate Liberty models, and collaborate with design teams to meet timing, power, and reliability targets for next-gen memory architectures.

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