Design Engineer I

Cadence Design Systems; Cary (NC); On-site; USD 89,000 - 165,000; Full time

Benefits offered by this job

Paid vacation

401(k) plan

Employee stock purchase plan

Medical, dental and vision plans

And more

Job summary

Cadence Design Systems seeks an experienced DFT engineer to define and implement SoC-level DFT across large designs. You will develop, integrate, and support SCAN, ATPG, MBIST, BSCAN and iJTAG while driving pre-silicon sign-off and post-silicon debugging.

Collaboration with RTL, verification, physical design and operations teams is essential to success. The role emphasizes hands-on DFT, strong problem solving, and the ability to operate within a cross-functional engineering environment.

Qualifications

• BS degree and at least 3 years of hands-on experience in SoC DFT.
• Strong expertise in SCAN, ATPG, MBIST.
• Experience with pre-silicon validation and post-silicon debug.
• Ability to collaborate with RTL, verification, physical design and operations teams.

Responsibilities

• Define and implement SoC level DFT architecture for large and complex designs.
• Develop, integrate, and support SCAN, ATPG, MBIST, BSCAN and iJTAG.
• Perform DFT insertion, verification, and coverage analysis at block and SoC levels.
• Drive pre-silicon DFT sign-off, including DRC closure and coverage targets.
• Support post-silicon debug, failure analysis and yield learning.
• Collaborate with RTL, verification, physical design and operation teams.

Skills

SCAN

ATPG

MBIST

Pre-silicon validation

Post-silicon debug

Cross-functional teamwork

Scripting (TCL, Python, Perl)

Education

Bachelor's degree

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are a small group of individuals designing among the most complex chip in the world getting into the award-winning Cadence Design Systems Palladium platform… As such we are seeking an experienced DFT engineer which role will span across the full spectrum of the DFT implementation: from architecture definition through silicon testing and debug. A bonus, this individual will have cross functional teams’ interactions not only within our group; but across Cadence and the multiple BU involved in our developments.

Key Responsibilities

• Define and implement SoC level DFT architecture for large and complex designs.
• Develop, integrate, and support SCAN, ATPG, MBIST, BSCAN and iJTAG.
• Perform DFT insertion, verification, and coverage analysis at block and SoC levels.
• Drive pre-silicon DFT sign-off, including DRC closure and coverage targets.
• Support post-silicon debug, failure analysis and yield learning.
• Collaborate with RTL, verification, physical design and operation teams.

Qualifications

• BS degree At least 3 years of hands-on experience in SoC DFT.

Must-have skills

• Strong expertise in SCAN, ATPG, MBIST.
• Experience with pre-silicon validation and post-silicon debug.
• Strong problem solving and debugging skills.
• Ability to work effectively in a cross-functional engineering environment.

Good-to-have skills

• Scripting experience (TCL, Perl, Python or equivalent) for flow automation and analysis.
• Experience with IP-level DFT integration and reuse.
• Exposure to low-power DFT considerations and complex clocking architectures.
• Familiarity with manufacturing test flows and silicon yield improvement.

The annual salary range for California is $88,900 to $165,100. You may also be eligible to receive incentive compensation: bonus, equity, and benefits.

Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.

Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.

Benefits

• paid vacation and paid holidays
• 401(k) plan with employer match
• employee stock purchase plan
• a variety of medical, dental and vision plan options
• and more

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