Lead Design Engineer

Cadence Design Systems, Inc.; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Cadence Design Systems is hiring a digital design engineer in Austin, TX. You will design and integrate IPs for SoC projects based on customer specs, perform lint/CDC checks, and create synthesis constraints to optimize power, performance, and area.

The role supports verification and physical design teams and emphasizes automation. Required 5+ years in digital design with Verilog/SystemVerilog, AMBA protocols, and scripting skills.

Qualifications

• B.E./B.Tech./M.Tech in Electronics/CS required.
• 5+ years of experience as a digital design engineer.
• Strong knowledge of digital design fundamentals and Verilog/SystemVerilog.
• Familiarity with Lint/CDC tools and ability to set up flows from scratch.
• Experience with AMBA protocols and other ARM IPs is a plus.

Responsibilities

• Design and integration of IPs in SoC based on customer specifications.
• Perform Lint/CDC checks and resolve issues.
• Create synthesis constraints at IP/SoC level and perform basic synthesis for PPA optimization.
• Create detailed Microarchitectural Specification documents.
• Support verification test plans, coverage analysis and debugging.
• Assist physical design team during implementation.
• Automate repetitive tasks and drive cross-team collaboration.

Skills

Digital design

Verilog

SystemVerilog

Scripting (Python/Perl/Tcl)

Cross-functional collaboration

Innovation/automation

Education

B.E./B.Tech/M.Tech in Electronics/CS

Tools

Lint/CDC tools

Synthesis tools

Xcelium

Verisium

AMBA protocols

PCIe/Ethernet/DDR

Static Timing Analysis (STA)

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Responsibilities

• Design and integration of IPs in SoC based on high-level architectural specifications from customers.
• Perform Lint/CDC checks on the design for quality assurance and resolve related issues.
• Create synthesis constraints for the design at the IP and SoC level and perform basic synthesis for PPA (Power, Performance, Area) optimization.
• Create detailed Microarchitectural Specification documents for the design.
• Provide support to the verification team for test plan creation, coverage analysis, and feature debugging.
• Provide support to the physical design team as needed for design implementation.
• Implement innovative solutions to automate repetitive tasks.
• Collaborate within and across teams for effective project execution.

Requirements

• B.E./B.Tech/M.Tech with at least 5 years of experience as a digital design engineer.
• Strong knowledge of digital design fundamentals and Verilog/SystemVerilog (SV).
• Solid knowledge of Lint/CDC tools and the ability to set up flows from scratch.
• Knowledge of creating synthesis constraints and Static Timing Analysis (STA); familiarity with synthesis tools is a plus.
• Familiarity with simulation tools (e.g., Xcelium, Verisium) to support verification.
• Experience with AMBA protocols and other ARM IPs is a plus.
• Experience with high-speed IPs such as PCIe, Ethernet, and DDR is a plus.
• Proficiency in scripting languages (Python/Perl/Tcl).
• Ability to innovate and automate repetitive tasks.
• Good communication skills for effective cross-functional collaboration.

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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For.

Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.