Customer Engagement Engineer II

Cadence Design Systems; San Jose, Northern (CA, KY); Hybrid; USD 105,000 - 195,000; Full time

Benefits offered by this job

Paid vacation

Paid holidays

401(k) with employer match

Employee stock purchase plan

Medical/Dental/Vision

Job summary

Cadence Design Systems is seeking a Customer Engagement Engineer II in San Jose. You will support Palladium, Protium, and PDAPP products, handling customer cases, testing fixes, and coordinating with R&D and field teams to ensure successful issue resolution.

The role requires a BS/EE or CE with 1+ years in design/verification, strong HDL and scripting skills, and good communication. Travel may be required. Competitive salary and benefits in California.

Qualifications

• BS or higher in Electrical Engineering or Computer Engineering.
• Proficient in HDL languages and design debugging techniques.
• Familiar with verification methodologies in EDA environments.

Responsibilities

• Handle incoming SFDC cases from field AEs and customers.
• Test R&D fixes/patches and collect collateral/test cases.
• Track customer metrics in JIRA and generate quality reports.

Skills

Verilog / SystemVerilog

VHDL

Unix scripting

Test case creation

Digital design

UVM

PCIe/USB/Ethernet

Education

BS in EE/CE

Tools

Cadence Palladium

Job description

## Customer Engagement Engineer IIApply: SAN JOSE: Full time: Posted Today: End Date: December 31, 2026 (30+ days left to apply): R56482## **At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.**As an integral member of the HSV Customer Support Team, you will work with our customers and field AE teams and R&D groups to provide technical support for our Palladium, Protium and Virtual Protocol (PDAPP) products. You will enjoy the experience and challenge in working with a broad spectrum of designs and customers. **Responsibilities includes:*** Handling incoming SFDC cases reported by field AEs and customers.* Report any tool bugs to R&D and work with field AE and customer to collect necessary collaterals and/or testcases.* Test R&D fixes/patches.* Tracking customer metrics in JIRA system, generating quality report for management.* undefined**Position Requirements:**Requires a BS-EE/CE (MS-EE/CE preferred) with a minimum of 1 years experience in design and/or verification of complex digital designs, or Applications engineering/technical support role.General knowledge of design debug techniques and a strong understanding in logic design.General knowledge in verification methodologies for complex EDA environments.Proficiency in HDL language like Verilog, System Verilog and VHDL. Ability to create test cases to replicate customer issues quickly.Proficiency in Unix/Linux scripting languages (ksh/bash/csh).Experience with emulation, Cadence's Palladium product preferred.General knowledge in TBA, SVA, SV coverage, Low Power(UPF). UVM experience is a plus.General knowledge in PCIe, USB and Ethernet protocol.Excellent communication skills. Must have ability to communicate complex issues to internal teams and customers in a clear and concise manner.Occasional travel may be required to resolve critical customer issues.undefined*The annual salary range for California is $105,000 to $195,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.*