Sr Principal Design Engineer

Cadence Design Systems; San Jose (CA); Hybrid; USD 154,000 - 286,000; Full time

Benefits offered by this job

401(k) plan with employer match

Employee stock purchase plan

Paid vacation and holidays

Medical, dental and vision options

Job summary

Cadence Design Systems in San Jose, CA is seeking a Sr Principal Design Engineer to lead mixed-signal circuit design, verification, and testing for high-speed serial-link IP. The role requires a Ph.D.

in EE with 5+ years or MS in EE with 7+ years in advanced process technologies, and strong collaboration with the digital team to meet performance targets. The ideal candidate will drive architectural decisions, develop test plans, and contribute to product readiness with excellent communication

Qualifications

• Ph.D. in Electrical Engineering with 5+ years or MS in EE with 7+ years of mixed-signal design in advanced process technologies.
• Strong communication skills and ability to lead technical discussions.
• Experience with mixed-signal design, verification, and testing methodologies.

Responsibilities

• Design and verify mixed-signal circuits from high-level architectural specs.
• Develop post-silicon test plans and drive closure of functional and performance targets.
• Collaborate with digital team to integrate with serial-link IP.
• Contribute to all phases of design, verification, and testing.

Skills

Mixed-signal design

Design verification flows

Post-silicon test planning

Signal processing concepts

C to support architecture

Python/Perl scripting

SystemVerilog/VerilogA

Education

Ph.D. EE (5+ years)

MS EE (7+ years)

Tools

Cadence analog design environment

MATLAB

SystemVerilog/VerilogA

Job description

## Sr Principal Design EngineerApplylocations: SAN JOSEtime type: Full timeposted on: Posted Yesterdayjob requisition id: R54907## **At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.**This is an opportunity to join a dynamic team of experienced engineers developing physical IP for industry-standard high-speed serial-links.The successful candidate will ideally be a highly-motivated self-starter who can work independently to complete assigned tasks and contribute to project leadership. The candidate will contribute to all mixed-signal design, verification, and testing aspects. This includes circuit design and development from a high-level architectural specification, post-silicon test plan development and execution, and collaboration with the digital team to achieve functional and performance closure.**Candidate must have a thorough understanding of the following:*** Mixed-signal circuit design fundamentals* Mixed-signal circuit design and verification flows* Cadence analog design environment* Basic signal processing concepts**Familiarity with the following items is a plus:*** Serial link design techniques* Data converter (ADCs and/or DACs) and/or clock synthesis and recovery (PLLs, DLLs, CDRs) techniques* MATLAB or C to facilitate architecture development* Hardware description languages such as SystemVerilog or VerilogA for functional model development* Scripting languages such as Perl or Python for automation* Silicon validation testing knowledge and experience**Other requirements:*** Excellent verbal and written communication skills* Ph.D. EE degree with 5+ years or MS EE. degree with 7+ years of mixed signal design industry experience in advanced process technologies*The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.*