Customer Engagement Engineer II

Cadence; San Jose (CA); On-site; USD 105,000 - 195,000; Full time

Job summary

Cadence is seeking an HSV Customer Support Team member to provide technical support for Palladium, Protium and Virtual Protocol (PDAPP) products in California. You will collaborate with field AEs, R&D, and customers to resolve design and verification issues, run tests, and generate quality reports.

The role requires a BS-EE/CE (MS preferred), strong HDL skills (Verilog/SystemVerilog/VHDL), and Unix scripting ability. Travel may be required. Salary ranges reflect California markets.

Qualifications

• BS-EE/CE degree required; MS-EE/CE preferred.
• 1+ year experience in design/verification or applications engineering/tech support.
• Strong knowledge of logic design and verification methodologies for complex EDA.
• Proficiency in HDL languages: Verilog, SystemVerilog, VHDL.
• Unix/Linux scripting languages (ksh/bash/csh).
• Experience with emulation; Palladium product is a plus.
• UVM experience is a plus.

Responsibilities

• Handle incoming SFDC cases reported by field AEs and customers.
• Report tool bugs to R&D and work with field AE and customer to collect collaterals/testcases.
• Test R&D fixes/patches.
• Track customer metrics in JIRA and generate reports for management.
• Occasional travel may be required to resolve critical customer issues.

Skills

Communication

Verilog

SystemVerilog

VHDL

Unix scripting

UVM

PCIe

Debug techniques

Travel

Education

BS-EE/CE

MS-EE/CE

Tools

Cadence Palladium

JIRA

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

As an integral member of the HSV Customer Support Team, you will work with our customers and field AE teams and R&D groups to provide technical support for our Palladium, Protium and Virtual Protocol (PDAPP) products. You will enjoy the experience and challenge in working with a broad spectrum of designs and customers.

Responsibilities Includes

• Handling incoming SFDC cases reported by field AEs and customers.
• Report any tool bugs to R&D and work with field AE and customer to collect necessary collaterals and/or testcases.
• Test R&D fixes/patches.
• Tracking customer metrics in JIRA system, generating quality report for management.
• undefinedPosition Requirements:Requires a BS-EE/CE (MS-EE/CE preferred) with a minimum of 1 years experience in design and/or verification of complex digital designs, or Applications engineering/technical support role.General knowledge of design debug techniques and a strong understanding in logic design.General knowledge in verification methodologies for complex EDA environments.Proficiency in HDL language like Verilog, System Verilog and VHDL. Ability to create test cases to replicate customer issues quickly.Proficiency in Unix/Linux scripting languages (ksh/bash/csh).Experience with emulation, Cadence's Palladium product preferred.General knowledge in TBA, SVA, SV coverage, Low Power(UPF). UVM experience is a plus.General knowledge in PCIe, USB and Ethernet protocol.Excellent communication skills. Must have ability to communicate complex issues to internal teams and customers in a clear and concise manner.Occasional travel may be required to resolve critical customer issues.undefined

The annual salary range for California is $105,000 to $195,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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