CPU Verification Director – Core & Memory Architect

Cadence Design Systems

San Jose (CA)

Hybrid

USD 186,000 - 345,000

Full time

14 days+

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Job summary

Cadence Design Systems seeks a Design Verification Architect / Director to lead the Processor Verification team in San Jose, CA, and Austin, TX. You will verify microprocessor cores and peripherals, craft verification plans, and implement testbenches and coverage monitors for highly complex CPU designs.

The role requires 17+ years in design verification, strong leadership, and deep knowledge of SystemVerilog/UVM.

Qualifications

  • 17+ years of design verification experience.
  • BS (or higher) in EE/Computer Engineering.
  • Proven experience at leading/managing team.
  • Strong managerial, leadership and interpersonal skills.
  • Excellent knowledge of computer architecture and design verification fundamentals.
  • Thorough understanding of SystemVerilog, UVM, and other programming languages to build flexible and reusable testbenches.
  • Exposure to scripting languages like Perl, Unix shell or similar languages.
  • Experience with assembly language programming required.
  • Experience with the development of fully automated flows.
  • Experience with Gate Level Simulations.
  • Excellent written and oral communication skills necessary.
  • Knowledge of processor verification required.

Responsibilities

  • Lead and run the Processor Verification team.
  • Verify microprocessor cores and their peripherals.
  • Craft verification plans and execute them for complex CPU designs.
  • Implement simulation/emulation testbenches, diagnostics, assertion checkers, and coverage monitors.
  • Record/track coverage and drive closure with cross-functional teams.
  • Coordinate with DV/Arch/Design/FW and manage a 7-10 engineer team.

Skills

Leadership
Management
Communication
Interpersonal skills
Computer architecture knowledge
SystemVerilog/UVM

Education

BS in EE/Computer Engineering

Tools

SystemVerilog
UVM
Perl
Unix shell
Formal Verification

Job description

Cadence Design Systems seeks a Design Verification Architect / Director to lead the Processor Verification team in San Jose, CA, and Austin, TX. You will verify microprocessor cores and peripherals, craft verification plans, and implement testbenches and coverage monitors for highly complex CPU designs.

The role requires 17+ years in design verification, strong leadership, and deep knowledge of SystemVerilog/UVM.

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