Senior SystemVerilog Verification Engineer (UVM/C++)

Arrow Enterprise Computing Solutions; San Jose (CA); Sur place; USD 140 000 - 190 000; Plein temps

Avantages offerts par ce poste

Medical, Dental, Vision Insurance

401k with Matching Contributions

Short-Term/Long-Term Disability

HSA/HRA Options

Paid Time Off

Tuition Reimbursement

Growth Opportunities

Résumé du poste

eInfochips, an Arrow company, is seeking a Design Verification Engineer in San Jose, CA. The candidate should have 6+ years of experience with SystemVerilog HVL and C/C++, plus UVM and SVTB/UVM proficiency.

Responsibilities include test plan development, BFM/Driver/Monitor/Scoreboard creation, integration in test benches, stress testing, and coverage closure. Experience with C++ testbenches and scripting (Make/Perl/Python) is required; DSP knowledge is a plus.

Qualifications

• 6+ years of experience in SystemVerilog HVL and C/C

Responsabilités

• Develop test plans and BVF/Driver/Monitor/Scoreboard components
• Build and integrate verification components in testbench
• Perform stress and corner testing, debug failures and achieve coverage closure
• Proficient in SVTB/UVM and C++ testbench
• Support verification closure with team

Connaissances

SystemVerilog HVL

C/C++

UVM

C++ testbench

Scripting (Make/Perl/Python)

Debug/assertions

Testbench integration

Outils

Subversion

Bugzilla

Description du poste

eInfochips, an Arrow company, is seeking a Design Verification Engineer in San Jose, CA. The candidate should have 6+ years of experience with SystemVerilog HVL and C/C++, plus UVM and SVTB/UVM proficiency.

Responsibilities include test plan development, BFM/Driver/Monitor/Scoreboard creation, integration in test benches, stress testing, and coverage closure. Experience with C++ testbenches and scripting (Make/Perl/Python) is required; DSP knowledge is a plus.