Senior SystemVerilog Verification Engineer - UVM & RTL

Highbrow Technology Inc; San Jose (CA); Sur place; USD 120 000 - 170 000; Plein temps

Description du poste

The candidate must have experience using SystemVerilog and UVM, designing verification components including UVM agents, checkers, and behavioral models. Experience with implementing and achieving coverage goals by developing random & directed test cases, and SystemVerilog Assertions. This engineer will be responsible for analyzing and debugging simulation failures at the RTL and gate-level. The engineer must be knowledgeable of RTL, gate level netlists, and SDF and capable of analyzing such formats in the verification context.

Requirements

• 7+ years of experience with verification concepts and architectures for complex digital and MXS circuits
• Experience verifying designs at the block and system levels.
• Experience with complex digital and mixed-signal circuits (PLL, DLL, ADC, DAC)
• Experience debugging RTL and gate-level netlists, analyzing schematic diagrams of analog / MXS circuits
• Experience using SystemVerilog and advanced verification concepts and methodologies (UVM, SVA)
• Experience with Synopsys, Cadence, and Mentor simulations tools
• Demonstrated ability to plan and deploy complex, reusable, and scalable verification environments
• Experience with Perl/Python and Tcl or other scripting languages
• Experience with version control systems (DesignSync, git)
• Superior writing, grammar, and verbal communication skills
• Excellent problem solver; develops and employs automated processes where applicable
• Worked independently and in a global team and dynamic environment in a highly visible role
• Possesses ability to learn and adapt to new tools and methodologies on the fly
• Must have legal authorization to work in the US

It is a plus if the candidate has expertise in one or more of the following areas:

• Experience with hardware design and debug
• Experience with emulation (Palladium, Veloce, Zebu) and FPGA (Xilinx) platforms
• Formal verification concepts / experience is a plus
• Experience with verifying iJTAG network using ICL and PDL in the Tessent tool a plus
• Experience with co-simulation a plus

Education and Experience required:

• BS in Electrical Engineering / Computer Engineering and 8+ years of related experience
• or an MS in Electrical Engineering / Computer Engineering and 6+ years of related