Sr Physical Design Engineer (GF 12LP) – 100% remote

Encore Semi, Inc.; Austin (TX); Remote; USD 135,000 - 165,000; Full time

Benefits offered by this job

15 days PTO

10 holidays

Medical benefits 80% premiums

Dental & Vision 50% premiums

Life Insurance

401k

Tuition reimbursement

Job summary

Encore Semi, Inc. is seeking a Senior Physical Design Engineer to lead RTL-to-GDSII implementation of high-performance SoCs.

You will own advanced FinFET design challenges, push PPA boundaries, and drive robust timing closure targeting the GlobalFoundries 12LP node. You will manage floorplanning, CTS, routing, STA, and reliability tasks using Fusion Compiler, PrimeTime, and StarRC, while building Tcl and Python scripts to streamline flows and track key metrics.

Qualifications

• 5+ years of ASIC physical design experience with tape-outs on FinFET nodes (≤14nm/12nm).
• Strong grounding in synthesis, CTS, SDC constraints, and signoff methodologies.
• BS or MS in Electrical/Computer Engineering or related field.

Responsibilities

• Drive block- and top-level physical design from synthesis through GDSII signoff using Fusion Design Platform.
• Execute floorplanning, power grid design, placement, CTS, and routing for GF 12LP architectures.
• Lead STA, parasitic extraction, and multi-corner/multi-mode closure with PrimeTime/StarRC.
• Address FinFET challenges, DRC/LVS, EM/IR-drop analysis, and reliability.
• Develop Tcl and Python scripts to streamline flows and improve PPA metrics.

Skills

ASIC physical design

Scripting (Tcl/Python/Perl)

Education

BS or MS in Electrical/Computer Engineering

Tools

Synopsys Fusion Compiler/ICC II

PrimeTime

StarRC

Job description

Full-time: Salary + Benefits + Bonuses / Contractor

Work Status: US Citizen required.

Location: Remote, anywhere in USA

About The Role

We are seeking a Senior Physical Design Engineer to lead the RTL-to-GDSII implementation of high-performance SoCs. In this role, you will take ownership of advanced FinFET design challenges, push Power, Performance, and Area (PPA) boundaries, and drive robust timing closure targeting the GlobalFoundries 12LP node.

What You’ll Do

• End-to-End Implementation: Drive block- and top-level physical design from synthesis through GDSII signoff using the Synopsys Fusion Design Platform.
• Core P&R & Optimization: Execute floorplanning, power grid design, placement, Clock Tree Synthesis (CTS), and detail routing optimized for GF 12LP standard cell architectures.
• Timing & Signoff: Lead Static Timing Analysis (STA), parasitic extraction, and multi-corner/multi-mode closure using PrimeTime and StarRC.
• Physical Verification & Reliability: Resolve advanced FinFET physical challenges, including double patterning, DRC/LVS (ICV), and EM/IR-drop analysis (RedHawk).
• Automation: Develop Tcl and Python scripts to streamline flows, improve runtimes, and track PPA metrics.

What You Bring

• Experience: 5+ years of ASIC physical design experience with proven tape-outs on advanced FinFET nodes (≤14nm/12nm).
• Tool Expertise: Deep hands-on proficiency with Synopsys Fusion Compiler (or ICC II) and PrimeTime.
• Technical Mastery: Strong grounding in synthesis, CTS, complex SDC constraints, and signoff methodologies.
• Scripting: Solid scripting skills in Tcl, Python, or Perl.
• Education: BS or MS in Electrical Engineering, Computer Engineering, or a related field.

Nice-to-Haves

• Direct tape-out experience on GF 12LP / 12LP+.
• Deep knowledge of advanced low-power flows (UPF, multi-voltage, DVFS).
• Experience hardening high-frequency processor cores (e.g., ARM, RISC-V)

The anticipated annual base salary for this position is between $135,000 to $165,000, which also includes a comprehensive benefits package.

Full-Time Benefits

• 15 days of PTO per calendar year
• 10 paid Holidays per calendar year
• Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
• Dental & Vision: Company covers 50% of premiums for Employee and Dependents
• Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance
• Employee Assistant Program (EAP)
• 401k - Traditional & Roth
• Life/AD&D and Long-Term Disability
• Tuition reimbursement

Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.

Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.

LinkedIn :: https://www.linkedin.com/in/rtl2gds/