Physical Design Engineer

Sintegra Inc.; San Francisco (CA); Sur place; USD 120 000 - 170 000; Plein temps

Résumé du poste

An innovative technology company in California is seeking an experienced Chip-Level / SoC-Level Design Engineer to join their team. The successful candidate will work on RTL-to-GDSII designs and contribute to SoC-top projects, utilizing tools like Fusion Compiler and ICC2. Key responsibilities include block-level design, scripting in TCL and Python, and working with multi-power domain designs. Familiarity with lower-node technologies is a strong advantage. This role presents an exciting opportunity to innovate within state-of-the-art engineering environments.

Qualifications

• Expertise in RTL-to-GDSII design processes at both block-level and top-level integration.
• Understanding of lower-node technologies (3nm, 4nm, 5nm) is a strong advantage.

Responsabilités

• Perform block-level and chip-level design from RTL-to-GDSII.
• Utilize the Synopsys Implementation tool suite (Fusion Compiler, ICC2).
• Conduct structural implementation and design with multi-power domains.

Connaissances

Proficiency with Synopsys Implementation tool suite

Strong scripting skills in TCL

Strong scripting skills in Python

Experience in block-level and chip-level design

Familiarity with multi-power domain design

Outils

Fusion Compiler

ICC2

Description du poste

We are seeking an experienced and highly skilled Chip-Level / SoC-Level Design Engineer to join our innovative team. The ideal candidate will excel in RTL-to-GDSII design processes across both block-level and top-level integration, demonstrating expertise in advanced implementation tools and techniques. This role offers the opportunity to work on cutting-edge designs for lower nodes (3nm, 4nm, 5nm) and contribute to full-chip and SoC-top projects.

Key Responsibilities

• Perform block-level and chip-level design from RTL-to-GDSII.
• Handle synthesis, floor-planning, place & route, timing/EMIR/PV closure, and signoff at both block and SoC-top levels.
• Utilize the Synopsys Implementation tool suite (Fusion Compiler, ICC2).
• Implement controllers for High-Speed IO IPs and integrate them at SoC-level.
• Conduct structural implementation, including datapaths, bus planning, and routing across chip-level hierarchies.
• Design with multi-power domains and ensure proper integration at SoC-top.
• Develop and maintain scripts using TCL and Python to support automation at block and chip-level.

Requirements

• Proficiency with Synopsys Implementation tool suite (Fusion Compiler, ICC2).
• Experience in structural implementation of datapaths, bus planning, and routing at block and chip-level.
• Strong scripting skills in TCL and Python.
• Familiarity with multi-power domain design and SoC-top integration.
• Experience with controllers for High-Speed IO IPs and their chip-level integration.
• Knowledge of lower-node technologies (3nm, 4nm, 5nm) is a strong advantage.