Principal Physical Design Engineer

Celero Communications, Inc.; Irvine (CA); On-site; USD 200,000 - 300,000; Full time

Job summary

Celero Communications, Inc. is seeking a Principal Physical Design Engineer to own the RTL-to-GDSII flow for complex SoCs and drive design convergence with frontend teams.

Responsibilities include floor planning, CTS, power-grid design, EM/IR cleanup, signoff STA and physical verification, and scripting to automate flows.

Qualifications

• 7+ to 15+ years of ASIC physical design experience.
• Deep tapeout experience in 7nm/5nm/3nm nodes.
• Proficiency with Cadence tools: Innovus, Tempus, Voltus, Pegasus, Calibre.
• Expertise in physically aware synthesis, power domain analysis, and EM/IR cleanup.

Responsibilities

• RTL-to-GDSII execution ownership for SoCs or complex blocks.
• Floor planning, bump planning, power grid design, and clock tree synthesis optimization.
• Resolve timing, congestion, EM/IR issues with frontend designers.
• Signoff & verification: STA and physical verification; fix DRC/LVS violations.
• Drive automation with Tcl, Python, or Perl to improve flows.
• Partner with architects, logic designers, and analog team for tapeout readiness.

Skills

ASIC physical design

Tapeout experience

EM/IR analysis

Scripting (Tcl/Python/Perl)

Cross-functional leadership

Education

Bachelor's / MS in EE

Tools

Cadence Innovus

Cadence Tempus

Cadence Voltus

Calibre

Pegasus

Job description

Principal Physical Design Engineer

• RTL-to-GDSII Execution: Own physical implementation of System-on-Chips (SoCs) or complex digital blocks.
• Design Optimization: Manage floor-planning, bump planning, power grid design, and clock tree synthesis (CTS) to optimize chip performance.
• Design Convergence: Resolve timing, congestions, EM/IR issues together with Frontend Designers
• Signoff & Verification: Run Static Timing Analysis (STA) and physical verification. Fix Design Rule Checking (DRC) and Layout Versus Schematic (LVS) violations.
• Methodology Development: Drive automation and improve flow robustness using scripting languages like Tcl, Python, or Perl.
• Cross-Functional Leadership: Partner with architects, logic designers, and analog design team for tapeout readiness.

Key Qualifications

• Experience: 7+ to 15+ years of relevant ASIC physical design experience (depending on degree level).
• Process Knowledge: Deep tapeout experience in advanced technology nodes (e.g., 7nm, 5nm, 3nm).
• Tool Mastery: Advanced proficiency with industry-standard EDA tools from vendors like Cadence (e.g., Innovus, , Tempus, Voltus, Pegasus, Calibre).
• Technical Concepts: Expertise in physically aware synthesis, power domain analysis, and Electromigration/IR-drop (EM/IR) cleanup.

Annual Base Salary Range: $200,000 to $300,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)