ASIC Design Engineer – Clocks IP

NVIDIA Corporation; Santa Clara (CA); On-site; USD 116,000 - 219,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation is seeking an ASIC Clocking Engineer to architect the clock domain for GPU/CPU, balancing functional, physical and testing requirements. You will collaborate across design, floorplanning, and lab teams to deliver robust clocking solutions and improve PPA across DFx, timing, and power.

You will work with Verilog RTL, verification and scripting to implement scalable clocking topologies, contributing to silicon bringup and end-to-end ASIC cycles.

Qualifications

• BS in Electrical Engineering or equivalent; MS preferred.
• 2+ years of relevant ASIC/clocking experience.
• Understanding of logic optimization and PPA trade-offs.
• Experience in RTL design (Verilog), verification and logic synthesis.
• Strong Python or scripting language skills.
• Knowledge of sub-micron silicon issues (noise, cross-talk, OCV) a plus.
• Experience with on-chip clocking networks is a bonus.

Responsibilities

• Architect the clock domain to satisfy functional, physical and testing design requirements.
• Engage with multiple teams to design GPU/CPU clocks meeting constraints.
• Improve Power, Performance and Area (PPA) across DFx, Physical Implementation, and timing.
• Collaborate with Physical, timing, and DFT teams to deliver clock RTL to verification.
• Participate in end-to-end ASIC cycle from micro-arch to silicon bringup.

Skills

RTL design

Python scripting

PPA trade-offs

Interpersonal collaboration

Verilog

Clocking networks knowledge

Silicon timing issues awareness

Education

BS in Electrical Engineering or equivalent

Job description

The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and CPU clocking. The team collaborates with the front design team to understand the clocking requirements for the chip. The clocks team interacts with the floor-planning and back end team to help craft the physical floorplan of the chip. The team explains the programming model to the SW team to come up with an efficient clock programming sequence. The team works with the silicon solution team to triage silicon or programming bugs in the lab. NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can take on, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence.

We have some of the most brilliant people in the world working for us and, due to unprecedented growth, our teams are rapidly growing.

What you’ll be doing:

As a Clocks team member, you will be architecting the clock domain to satisfy functional, physical and testing design requirements. Engage with multiple teams and design the GPU or CPU clocks to satisfy all the architectural/design/physical constraints. Improve Power, Performance, and Area (PPA) of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL. Collaborate with Physical design and timing team to evaluate Clocking concerns and develop solutions for supporting high speed Clocking. Together with other team members, we deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams. Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.

What we need to see:

• BS in Electrical Engineering or equivalent experience (MS preferred) 2+ years of relevant work experience.
• Deep understanding of logic optimization techniques and PPA trade-offs.
• Excellent interpersonal skills and ability to collaborate with multiple teams.
• Experience in RTL design (Verilog), verification and logic synthesis.
• Strong coding skills in python or other industry-standard scripting languages.
• Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus.
• Implementing on-chip clocking networks is a bonus.

Ways to stand out from the crowd:

• Experience with clocks controller, clocks logic design
• Understanding of system level artifacts like power, noise, etc
• Experience with scalable designs and architecture.
• Hands- on silicon debug is a plus.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3. You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until September 14, 2026. This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer.

As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

NVIDIA pioneered accelerated computing. Today, our AI infrastructure powers global intelligence, transforming every industry.

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