Clock-Gen IP Verification Engineer (Pre-Silicon)

Intel Corporation; Hillsboro (OR); Hybrid; USD 122,000 - 173,000; Full time

Benefits offered by this job

Competitive pay

Stock bonuses

Health benefits

Retirement plan

Vacation

Job summary

Intel Corporation's Central Engineering Group seeks an IP Design Verification Engineer in Hillsboro, Oregon to verify clock generator IPs (PLL/FLL) through pre-silicon stages. You will develop verification environments, tests, and documentation using SystemVerilog and UVM.

Collaborate with architects, RTL and analog teams to refine verification approaches across IP generations and lead AMS validation activities, ensuring high-quality, scalable IP designs for Intel's next-generation products.

Qualifications

• Bachelor's or higher in Electrical or Computer Engineering or related field with 4+ years of experience; or Master's with 3+ years; or PhD with 1+ year.
• 2+ years in design verification and validation methodologies, including UVM, System Verilog, and industry-standard EDA tools.
• Scripting in Python and Perl.

Responsibilities

• Develop test benches, verification environments, and tests using SystemVerilog and UVM for IP validation.
• Perform functional verification of PLL/FLL clock generator IPs per specifications.
• Maintain and refine verification infrastructure across IP generations.
• Debug and root-cause pre-silicon issues within verification environments.
• Document test plans and participate in technical design reviews.
• Collaborate with architects, RTL and analog design teams to improve verification of features.
• Lead Mixed Signal Validation activities including AMS simulations and schematic debugging.
• Contribute to architectural and microarchitectural feature definitions for IP design.

Skills

Design verification

SystemVerilog

UVM

Python

Perl

Education

Electrical or Computer Engineering degree

Tools

Industry-standard EDA tools

Job description

Intel Corporation's Central Engineering Group seeks an IP Design Verification Engineer in Hillsboro, Oregon to verify clock generator IPs (PLL/FLL) through pre-silicon stages. You will develop verification environments, tests, and documentation using SystemVerilog and UVM.

Collaborate with architects, RTL and analog teams to refine verification approaches across IP generations and lead AMS validation activities, ensuring high-quality, scalable IP designs for Intel's next-generation products.