Hybrid Pre-Silicon Verification Engineer (PLL/FLL)

Intel Corporation; Phoenix (AZ); Hybrid; USD 122,000 - 173,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Retirement plan

Vacation days

Job summary

Intel Corporation's Central Engineering Group is seeking an IP Design Verification Engineer to ensure the functional accuracy of clock generator IPs (PLL/FLL) throughout the product lifecycle. You will develop verification environments, write tests in SystemVerilog/UVM, and debug issues to meet stringent specifications.

Collaborating with architects, RTL and analog teams, you will maintain verification infrastructure and contribute to architectural features for IPs across multiple generations in

Qualifications

• Design verification and validation methodologies with UVM and System Verilog.
• Experience with Python and Perl scripting for test automation.
• Familiarity with industry-standard EDA tools and RTL concepts.

Responsibilities

• Develop test benches and verification environments using System Verilog and UVM.
• Perform functional verification for clock generator IPs (PLL/FLL) per specs.
• Maintain verification infrastructure across multiple IP generations and debug pre-silicon issues.

Skills

UVM

System Verilog

Python

Perl

EDA tools

Education

Bachelor's Degree in Electrical or Computer Engineering or related field

Master's Degree in Electrical or Computer Engineering or related field

PhD in Electrical or Computer Engineering or related field

Tools

System Verilog UVM coding

RTL development

AMS simulations

Job description

Intel Corporation's Central Engineering Group is seeking an IP Design Verification Engineer to ensure the functional accuracy of clock generator IPs (PLL/FLL) throughout the product lifecycle. You will develop verification environments, write tests in SystemVerilog/UVM, and debug issues to meet stringent specifications.

Collaborating with architects, RTL and analog teams, you will maintain verification infrastructure and contribute to architectural features for IPs across multiple generations in