Pre-Silicon IP Verification Engineer - RTL/UVM

Intel Corporation; Hillsboro, Northern (OR, KY); Hybrid; USD 106,000 - 200,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Retirement plan

Paid vacation

Job summary

Intel Corporation in Hillsboro, Oregon, seeks an experienced verification engineer to join the Logic Design and Validation group. You will build RTL tests and pre-silicon validation for next‑generation silicon using scalable UVM‑based environments.

You will define verification strategies, drive coverage, and debug pre‑silicon failures while collaborating with architecture, physical design and post‑silicon teams. Hybrid on-site/work model and detailed technical reviews are expected.

Qualifications

• Experience with Pre-silicon logic validation using SystemVerilog and UVM.
• Experience in Digital design using Verilog and/or SystemVerilog.
• Experience with pre-silicon validation closure across multiple projects.
• Hands-on experience with UVM testbench design for reusability and scalability.
• Experience with end-to-end validation strategies for complex digital systems.

Responsibilities

• Design and develop verification environments with scalable UVM testbenches.
• Define verification strategy and ensure coverage closure across projects.
• Develop RTL designs and integrate into SoC architectures with IP providers.
• Develop power verification methodologies for mixed-signal IPs.
• Create and apply SystemVerilog Assertions to strengthen coverage.
• Debug and root-cause pre-silicon failures and drive fixes.
• Collaborate across architecture, physical design and post-silicon teams.
• Incorporate post-silicon learnings into pre-silicon verification methodologies.
• Maintain detailed test plans and lead technical reviews.

Skills

SystemVerilog

UVM

Verilog

Digital design

Python scripting

SVA

Coverage-driven verification

Debugging

Communication

Education

Master's degree in Electrical Engineering or Computer Engineering

Bachelor's degree in Electrical Engineering or Computer Engineering

Tools

UPF

Simulation tools

UVM testbench design tools

Job description

Intel Corporation in Hillsboro, Oregon, seeks an experienced verification engineer to join the Logic Design and Validation group. You will build RTL tests and pre-silicon validation for next‑generation silicon using scalable UVM‑based environments.

You will define verification strategies, drive coverage, and debug pre‑silicon failures while collaborating with architecture, physical design and post‑silicon teams. Hybrid on-site/work model and detailed technical reviews are expected.