Pre-Silicon IP Verification Engineer - PLL/FLL Expert

Intel Corporation; Santa Clara (CA); Hybrid; USD 122,000 - 173,000; Full time

Job summary

Intel Corporation's Central Engineering Group is seeking an IP Design Verification Engineer to verify clock generator IPs (PLL/FLL) across Intel’s product lifecycle. You will build verification environments, write tests, and debug pre-silicon issues to ensure IPs meet stringent specifications.

The role emphasizes cross-functional collaboration with architects, RTL and analog teams, and leadership of Mixed Signal Validation activities to uphold high quality and performance in Intel's

Qualifications

• Bachelor's degree in Electrical or Computer Engineering or related field with 4+ years of experience (or Master’s with 3+ years; or PhD with 1+ year)
• Experience with design verification and validation methodologies including UVM, SystemVerilog

Responsibilities

• Develop test benches and verification environments using SystemVerilog and UVM
• Perform functional verification for clock generator IPs (PLL/FLL)
• Maintain and refine verification infrastructure for multiple IP generations
• Debug and root-cause pre-silicon issues in the verification environment
• Document test plans and participate in technical reviews with design teams
• Collaborate with architects, RTL developers, and analog design teams to verify architectural features
• Lead Mixed Signal Validation activities including AMS simulations and schematic debugging
• Contribute to the definition of architectural and microarchitectural features for IP design

Skills

SystemVerilog

UVM

Python

Perl

AMS simulations

Verification environments

Education

Bachelor's Degree in Electrical or Computer Engineering

Master's Degree in Electrical or Computer Engineering

PhD in Electrical or Computer Engineering

Tools

EDA tools

Job description

Intel Corporation's Central Engineering Group is seeking an IP Design Verification Engineer to verify clock generator IPs (PLL/FLL) across Intel’s product lifecycle. You will build verification environments, write tests, and debug pre-silicon issues to ensure IPs meet stringent specifications.

The role emphasizes cross-functional collaboration with architects, RTL and analog teams, and leadership of Mixed Signal Validation activities to uphold high quality and performance in Intel's