Signal & Power Integrity Engineer for AI/TPU Hardware

Google LLC; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Job summary

Google is seeking a Signal Integrity/Power Integrity Engineer in Sunnyvale to shape AI/ML hardware acceleration and TPU technology. You will lead chip and package design, ensure SI/PI performance, and drive co-design from concept to production within cross-functional teams across hardware and software.

You’ll collaborate with silicon, system, and vendor teams, advancing simulation methodologies and post-silicon validation for next-generation TPU architectures powering AI/ML workloads at scale.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related field, or equivalent practical experience.
• 8 years of experience in SI/PI design for chip/package or system PCB.
• Experience with industry SIPI modeling tool chains (HFSS, ADS, Sigrity, Siwave).
• Experience with lab bring-up, test environments, and characterization for high-speed memory and SerDes.
• Experience collaborating across chip architecture, physical design, STA, package, and validation teams.
• Proficiency in Python, MATLAB, or C++ to automate flows and data processing.

Responsibilities

• Lead SI and PI analysis and optimization for HPC using advanced 2.5D/3D packaging technologies.
• Collaborate early in product definition to influence chip floorplanning, PDN, nets, and routability tradeoffs.
• Evaluate high-speed interface IPs and develop memory interfaces across IO PHY, SI/PI, and physical design.
• Drive post-silicon validation and qualification for NPI while balancing SI/PI performance and DFM constraints.
• Partner with silicon, system, and vendor teams to develop simulation methodologies for modeling accuracy.

Skills

SI/PI design

Python

MATLAB

C++

Education

Bachelor's degree in EE/CS

Equivalent practical experience

Tools

HFSS

ADS

Sigrity

Siwave

Job description

Google is seeking a Signal Integrity/Power Integrity Engineer in Sunnyvale to shape AI/ML hardware acceleration and TPU technology. You will lead chip and package design, ensure SI/PI performance, and drive co-design from concept to production within cross-functional teams across hardware and software.

You’ll collaborate with silicon, system, and vendor teams, advancing simulation methodologies and post-silicon validation for next-generation TPU architectures powering AI/ML workloads at scale.