Senior SI/PI Engineer - Chip-Package-System Co-Design

Socket.dev; Sunnyvale (CA); On-site; USD 178,000 - 250,000; Full time

Job summary

Socket.dev is seeking a seasoned SI/PI Engineer to own chip-package-system co-design for AI accelerators and HPC silicon. You will drive SI/PI requirements from architecture through post-silicon validation across 2.5D/3D packaging with interposers, wafer-on-wafer stacking, and high-density substrates.

You will collaborate with ASIC, package, PCB, and foundry teams to ensure high-speed interfaces and PDN meet performance and reliability targets before tape-out.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 8+ years of experience with signal integrity analysis, simulation, and measurement
• Proficient with HFSS, Sigrity, Hspice, and/or other simulation tools
• Familiar with impedance control, transmission line and PDN characterization, feasibility study and design guidelines
• Experience with 2.5D/3D package design (e.g., silicon interposer, silicon bridge, 3D die stacking, STA, voltage budget, simulation)
• Expertise in signal and power integrity for various high speed interconnects (HBMx, D2D, Ethernet, PCIe)
• Familiarity with post-Si test environment on memory and high-speed SERDES
• Familiarity with next-gen memory, chiplet standards and timing budgets
• Package-level SI/PI understanding across silicon, package, and board

Responsibilities

• Chip-Package-System Co-Design: drive SI/PI requirements from product definition to tape-out
• Die-Package-Board Co-Optimization across multiple chiplets
• Package SI/PI Ownership: substrate/interposer stack-up selection, design guide, post-layout sign-off
• High-Speed Interfaces: manage channels for HBM/HBM4/UHBM, UCIe, PCIe, Ethernet SerDes
• Power Delivery: analyze PDN AC+DC, impedance, decoupling, IR drop
• Simulation Flow: lead pre/post-layout SI/PI simulations and model development
• Timing & Budgets: maintain interface timing and voltage/noise budgets
• Tool & Flow Development: improve SI/PI flows via automation and modeling
• Validation Methodology: define SI/PI validation plans
• Post-Silicon: post-silicon validation and lab correlation
• Failure Analysis: support design validation on SI/PI failures
• Cross-functional collaboration across Architecture, ASIC, Mixed Signal, Package, PCB
• Engage foundries and OSATs on interconnect and die-stacking standards

Skills

Signal integrity

Power integrity

2.5D/3D package design

Impedance control

Transmission line theory

Education

Bachelor's degree in CS/CE or equivalent

Tools

HFSS

Sigrity

HSPICE

Job description

Socket.dev is seeking a seasoned SI/PI Engineer to own chip-package-system co-design for AI accelerators and HPC silicon. You will drive SI/PI requirements from architecture through post-silicon validation across 2.5D/3D packaging with interposers, wafer-on-wafer stacking, and high-density substrates.

You will collaborate with ASIC, package, PCB, and foundry teams to ensure high-speed interfaces and PDN meet performance and reliability targets before tape-out.