Chip Lead — Digital ASIC Architect & Tape-Out

Broadcom; San Jose (CA); On-site; USD 144,000 - 230,000; Full time

Job summary

Broadcom is seeking a hands‑on Principal Digital Design Engineer to serve as the Chip Lead for next‑generation silicon projects in San Jose. You will own the top‑level architecture, microarchitecture, and full chip integration, guiding cross‑disciplinary teams from definition to tape‑out.

You will drive RTL design using SystemVerilog/Verilog, set timing constraints, and oversee front‑end flows plus IP management. A strong track record of silicon success and leadership is essential.

Qualifications

• 12+ years of ASIC/SoC digital design experience with a track record of owning chip projects.
• Expert-level SystemVerilog/Verilog digital design and microarchitecture knowledge.
• Fluency with front-end EDA tools for synthesis, STA, and CDC analysis.
• Proven ability to deliver first-pass silicon on modern processes and strong communication.

Responsibilities

• Own top-level digital architecture and integration across blocks.
• Drive timing constraints and CDC strategy for the PD team.
• Lead front-end flows: synthesis, STA, linting, and CDC checks.
• Manage IP integration and collaborate with post-silicon validation.
• Provide mentorship and architectural guidance to engineers.

Skills

Chip lead

SystemVerilog/Verilog

Leadership

Communication

Education

Bachelor’s or Master’s in Electrical/Computer Eng

Tools

Front-end EDA tools (Synopsys/Cadence)

Job description

Broadcom is seeking a hands‑on Principal Digital Design Engineer to serve as the Chip Lead for next‑generation silicon projects in San Jose. You will own the top‑level architecture, microarchitecture, and full chip integration, guiding cross‑disciplinary teams from definition to tape‑out.

You will drive RTL design using SystemVerilog/Verilog, set timing constraints, and oversee front‑end flows plus IP management. A strong track record of silicon success and leadership is essential.