Lead Digital ASIC Architect - Chip Design Leader

Draper Labs; Cambridge (MA); On-site; USD 82,000 - 220,000; Full time

Benefits offered by this job

Work-life balance programs

Employee clubs

Discounts to museums

Job summary

Draper Labs in Cambridge, MA seeks a Senior Digital ASIC Architect to lead the design of digital ICs from concept to delivery. You will develop architectural concepts, model and simulate, and collaborate with analog and digital designers to optimize tradeoffs.

You will guide chip-level planning, drive SOC design decisions, mentor engineers, deliver technical solutions to customers, and contribute to verification, test planning, and documentation.

Qualifications

• Requires a bachelor's degree in Engineering or related field.
• 5–7 years of ASIC hardware experience with a bachelor's degree or 3–5 with a master's.
• Ability to write detailed design specifications and lead small teams.
• Strong verbal and written communication skills.
• Experience with IC design tools and top-level planning.

Responsibilities

• Independently drive IC-based solutions to complex customer problems.
• Design and simulate circuits from transistor-level to SOC implementations.
• Lead multidisciplinary design teams and mentor engineers.
• Participate in system-level design and verification planning.
• Develop design documentation and best practices.

Skills

IC design

Semiconductors

SystemVerilog

Team leadership

Communication

Architectural design

SOC design

Education

Bachelor's degree in Engineering or related field

Master's degree preferred

Tools

Cadence

Genus

Innovus

Tempus

Voltus

Job description

Draper Labs in Cambridge, MA seeks a Senior Digital ASIC Architect to lead the design of digital ICs from concept to delivery. You will develop architectural concepts, model and simulate, and collaborate with analog and digital designers to optimize tradeoffs.

You will guide chip-level planning, drive SOC design decisions, mentor engineers, deliver technical solutions to customers, and contribute to verification, test planning, and documentation.