STA Engineer

Apple Inc.

Cupertino (CA)

On-site

USD 140,000 - 210,000

Full time

14 days+

Get more replies from employers

Send a job-specific resume in minutes.

Job summary

Apple Inc. in Cupertino seeks an ASIC STA Engineer to lead timing closure across complex SoCs. You will own timing closure for full chips and blocks, guiding timing verification and constraint generation across projects.

Work with multi-functional teams to resolve timing issues in deep sub-micron technologies. Strong digital design fundamentals and scripting in TCL/Perl are valuable, with Primetime familiarity a plus.

Qualifications

  • Bachelor's degree with 3+ years in ASIC/STA timing.
  • Strong fundamentals in digital design and timing concepts.
  • Experience with timing tools such as Primetime is a plus.

Responsibilities

  • Own full chip and block timing closure across projects.
  • Develop timing verification methodologies and flows.
  • Generation of block and full chip timing constraints.
  • Collaborate with SOC teams to resolve complex timing issues.

Skills

Digital design
Self-starter
TCL scripting
Perl scripting
ASIC timing
STA tools
Synthesis flows
Constraint analysis
Cross-team comms

Education

Bachelor's degree + 3 years experience

Tools

Primetime
Galaxy Constraint Analyzer (GCA)

Job description

Imagine what you could do here at Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the unrivaled and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a hardworking engineer to join our exciting team of problem solvers. Come join our team and be responsible for leading edge IP development and coordinating with multiple SOC teams. In this role, you will work collaboratively with various SOC teams to execute design and integration tasks for the high quality IP deliverables.

Description

As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC design: Full chip and block level timing closure ownership throughout the entire project. Develop and maintain methodology and flows related to timing verification and closure. Generation of block and full chip timing constraints. Work on Apple SoC (System-on-Silicon) chips in deep sub-micron technologies targeted for high end mobile applications. Work closely with various multi-functional teams on resolving complex timing issues for major building blocks of complex SoCs.

Minimum Qualifications
  • Bachelors Degree + 3 Years of Experience.
Preferred Qualifications
  • Strong fundamentals in the area of Digital design
  • Self-starter and highly motivated
  • Proficient in scripting languages (TCL and Perl)
  • Familiarity with ASIC design timing concepts
  • Exposure in STA tools (Primetime) is a plus
  • Familiarity with front end tools and methodologies such as Synthesis, Logic equivalence checks
  • Familiarity in Constraint analysis and debug, using industry standard tools such as Synopsys GCA (Galaxy Constraint Analyzer) is desirable but not required
  • Knowledge of timing corners/modes, process variations and signal integrity related issues is a plus
  • Ability to commnicate optimally across all internal groups

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.

Learn about accessibility in Apple’s workplace

Learn about reasonable accommodations for job applicants

Apple accepts applications to this posting on an ongoing basis.

Get your free, confidential resume review.
or drag and drop your file here.
Similar jobs

Similar jobs worth comparing

STA Engineer
STA Engineer

Apple Inc. • Austin (TX)

On-site
USD 100,000 - 130,000
STA Engineer
STA Engineer

Apple Inc. • Austin (TX)

On-site
USD 90,000 - 120,000
Timing Design Engineer
Timing Design Engineer

Apple Inc. • San Diego (CA)

On-site
USD 122,700 - 214,300
ASIC Design Engineer
ASIC Design Engineer

Apple Inc. • Beaverton (OR)

On-site
USD 150,000 - 210,000
Timing Design Engineer
Timing Design Engineer

Apple Inc. • Waltham (MA)

On-site
USD 116,400 - 203,000
Employee stock purchase plan
Relocation assistance
Discretionary bonuses
ASIC Design Engineer
ASIC Design Engineer

Apple Inc. • Cupertino (CA)

On-site
USD 180,000 - 280,000
ASIC Design Manager
ASIC Design Manager

Apple Inc. • Cupertino (CA), Northern (KY)

Hybrid
USD 206,000 - 356,000
Stock plans
Retirement benefits
Education reimbursement
+1
Engineer Job Apple Boston
Engineer Job Apple Boston

Apple • Boston (MA)

On-site
SoC Systems Software Engineer
SoC Systems Software Engineer

Apple Inc. • Austin (TX)

On-site
USD 100,000 - 140,000
Cellular ASIC Design Engineer
Cellular ASIC Design Engineer

Apple Inc. • Austin (TX)

On-site
USD 130,000 - 160,000