SoC Physical Design Engineer, STA/Timing

Apple Inc.; Cupertino (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

Apple Inc. in Cupertino, CA, is seeking a SoC Physical Design Engineer focused on STA/Timing to drive timing closure for a highly complex SoC from netlist to tapeout.

You will collaborate with design and Physical Design teams to understand constraints, debug timing, create timing ECOs, develop scripts and methodologies, and document guidelines to improve performance and reliability.

Qualifications

• Bachelor's degree with 0+ years industry experience
• Experience with STA
• Experience with noise, crosstalk, and/or OCV effects

Responsibilities

• Work with design teams to understand and debug constraints and facilitate logic changes to improve timing.
• Work with the Physical Design team, highlighting issues and best practices.
• Help create timing ECO's for project tapeout.
• Create and maintain scripts and methodologies for analysis and runs.
• Create documentation and help with guidelines/specs.
• Deep analysis of timing paths to identify key issues.
• Implement timing infrastructure.

Skills

STA experience

Noise & crosstalk

Timing closure

Communicator

Education

Bachelor's degree

Tools

Perl

TCL

Job description

SoC Physical Design Engineer, STA/Timing

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it! Join us to help deliver the next groundbreaking Apple product.In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SoC using state of the art process technology.

Description

• Work with design teams to understand and debug constraints and facilitate logic changes to improve timing.
• Work with the Physical Design team, highlighting issues and best practices.
• Help create timing ECO's for project tapeout.
• Create and maintain scripts and methodologies for analysis and runs.
• Create documentation and help with guidelines/specs.
• Deep analysis of timing paths to identify key issues.
• Implement timing infrastructure.

Minimum Qualifications

• Minimum Bachelor's degree with 0+ years industry experience
• Experience with STA.
• Experience with noise, crosstalk, and/or OCV effects.

Preferred Qualifications

• Familiar with important aspects of timing of large high-performance SoC designs in sub-micron technologies.
• Experience with STA and methodologies for timing closure.
• Familiar with circuit modeling, including SPICE models, and/pr worst-case corner selection.
• Good programming skills with Perl and TCL.
• Experience with large design STA and Timing Closure.
• Familiar with ECO techniques and implementation.
• Good communicator who can accurately describe issues and follow them through to completion.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

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Apple accepts applications to this posting on an ongoing basis.