CAD Engineer - Timing for Gate-Level Flows & Methodologies

Apple Inc.; San Jose (CA); On-site; USD 140,000 - 180,000; Full time

Job summary

Apple Inc. is seeking a CAD Engineer focused on Timing for Gate-Level Flows & Methodologies in San Jose, CA. You will contribute to timing analysis, create and refine flows, and partner with design teams to drive first-time silicon success.

In this role you will develop and maintain gate-level STA flows, debug issues related to constraints and scripts, and work with EDA vendors to adopt new capabilities for performance and productivity gains. A BS degree and 3 years’ experience are required.

Qualifications

• BS degree and 3 years of relevant industry experience.
• Experience with static timing analysis tools and flows.
• Familiar with Python and Tcl or similar high-level languages.
• Knowledge of timing constraints and STA of large high-performance SoCs.
• Good communicator capable of cross-team collaboration.

Responsibilities

• Develop, maintain, and enhance existing gate-level STA flows for Apple silicon designs.
• Work with design teams to understand and debug issues related to constraints, flow scripts, and timing closure.
• Facilitate and drive STA methodology changes to improve STA flows, efficiency, productivity, and silicon timing correlation.
• Develop and maintain scripts and methods for timing analysis and power reduction.
• Develop and support methodologies, tools, and flows used in timing constraint verification, driving best practices across design teams.
• Analyze timing paths to identify key issues, including post-silicon timing debug.
• Collaborate with EDA vendors to incorporate new capabilities to solve technical problems.

Skills

Static timing analysis

Python

Tcl

SoC timing

Noise & Crosstalk

Education

BS degree

Tools

Flow scripting

EDA tools

Job description

CAD Engineer - Timing for Gate-Level Flows & Methodologies

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices! In this role as a member of the STA CAD team, you will be an integral part of the effort to improve the performance of Apple Silicon. You will be responsible for all aspects of static timing methodologies, addressing timing challenges on advanced tech nodes through the development of flows and methodologies used by all Apple Silicon teams in driving timing analysis and closure for first time right silicon.

Description

• Develop, maintain, and enhance existing gate-level STA flows for Apple silicon designs
• Work with design teams to understand and debug issues related to constraints, flow scripts, and timing closure
• Facilitate and drive STA methodology changes to improve overall STA flows as it relates to efficiency/productivity and silicon timing correlation
• Develop and maintain scripts and methods for timing analysis and power reduction
• Develop and support methodologies, tools, and flows used in the verification of timing constraints, drive best practices across design teams
• Analysis of timing paths to identify key issues, including post-silicon timing debug
• Work closely with EDA vendors to develop and incorporate new capabilities to solve technical problems

Minimum Qualifications

• Minimum requirement of BS and 3 years of relevant industry experience.

Preferred Qualifications

• Experience with static timing analysis tools and flows
• Understanding of programming fundamentals and concepts. Familiarity with Python and Tcl or other high level programming languages
• Familiar with STA of large high-performance SoC designs in deep sub-micron technologies
• Understanding of fundamentals in noise, cross-talk, variation and timing margins
• Knowledge of timing/SDC constraints, hands on experience in creation/validation a plus
• Good communicator who can accurately assess and describe issues to management as well as follow solutions through to completion

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

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Apple accepts applications to this posting on an ongoing basis.