SoC Physical Design Engineer, STA/Timing

Apple Inc.; Austin (TX); On-site; USD 150,000 - 230,000; Full time

Job summary

Apple Inc. in Austin, Texas seeks a SoC Physical Design Engineer, STA/Timing, to own the timing closure for a highly complex SOC from netlist to tapeout using state-of-the-art process technologies. You will collaborate with design and PD teams to optimize timing and implement ECOs.

BS with 10+ years of relevant experience and strong Perl/TCL scripting skills are required, with Hands-on STA and timing closure expertise preferred for high-performance SoCs.

Qualifications

• BS and 10+ years of relevant industry experience.
• Experience with large design STA and/or Timing Closure.
• Programming skills with Perl and TCL.

Responsibilities

• Work with design teams to understand and debug constraints and facilitate logic changes to improve timing.
• Work with the Physical Design team, highlighting issues and best practices.
• Help create timing ECO’s for project tapeout.
• Create and maintain scripts and methodologies for analysis and runs.
• Create documentation and help with guidelines/specs.
• Deep analysis of timing paths to identify key issues.
• Implement timing infrastructure.

Skills

STA experience

Timing closure

Education

Bachelor's degree

Tools

Perl

TCL

Job description

SoC Physical Design Engineer, STA/Timing

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it! Join us to help deliver the next groundbreaking Apple product. In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC using state of the art process technology.

Description

• Work with design teams to understand and debug constraints and facilitate logic changes to improve timing.
• Work with the Physical Design team, highlighting issues and best practices.
• Help create timing ECO’s for project tapeout.
• Create and maintain scripts and methodologies for analysis and runs.
• Create documentation and help with guidelines/specs.
• Deep analysis of timing paths to identify key issues.
• Implement timing infrastructure.

Minimum Qualifications

• Minimum BS and 10+ years of relevant industry experience.
• Experience with large design STA and/or Timing Closure.
• Programming skills with Perl and TCL.

Preferred Qualifications

• Hands-on experience in STA.
• Familiar with important aspects of timing of large high-performance SoC designs in sub-micron technologies.
• Proficient in STA and methodologies for timing closure and have a fundamental understanding of noise, crosstalk, and OCV effects, among others.
• Familiar with circuit modeling, including SPICE models, and worst-case corner selection.
• Familiar with ECO techniques and implementation.
• Good communicator who can accurately describe issues and follow them through to completion.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

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Apple accepts applications to this posting on an ongoing basis.