RTL2PD Design Engineer (ASIC)

Inabia-Software-; San Francisco (CA); On-site; USD 103,000 - 110,000; Full time

Job summary

Inabia-Software- in the Bay Area seeks an experienced RTL2PD Design Engineer to drive RTL synthesis, constraint writing, validation, and STA for ASIC flows, with scripting for RTL synthesis and STA. This onsite role requires deep hands-on expertise across 16nm/7nm nodes and collaboration with design teams.

Proficiency with Design Compiler, PrimeTime, Tempus, and Genus is essential. You will generate clean netlists and debug synthesis issues to meet timing objectives.

Qualifications

• 8–12 years of hands-on RTL Synthesis experience.
• Experience with 16nm and 7nm nodes is preferred.
• Visa-friendly; C2C engagements allowed.

Responsibilities

• RTL Synthesis, Constraint writing, validation, and STA.
• Write/modify scripts for RTL synthesis, SDC creation, and STA.
• Debug synthesis issues and STA to generate clean netlists.
• Perform RTL2PD tasks onsite in the Bay Area.

Skills

RTL Synthesis

Constraint Writing

Validation

STA

Scripting

Tools

Design Compiler

PrimeTime

Tempus

Genus

Job description

Hello,

Job Title : RTL2PD Design Engineer / RTL2PD Design Engineer (ASIC)

Client: Arrow Electronics

Experience Required: 8–12 years of hands-on experience

Pay Rate - $75/hr on W2 and $80/hr on C2C

Work Location:Bay Area, CA (Onsite)

Visa: All visa, except H1B transfer

C2C engagements are allowed.

RTL to Physical Design (RTL2PD) stage experience

MUST HAVE : RTL Synthesis, Constraint writing, validation, Static timing Analysis

What candidate will Be Doing:

RTL Synthesis, Constraint writing, validation, Static timing Analysis

Writing Scripts/Modiying scripts for RTL synthesis, SDC creation, STA

Debug synthesis issues and STA

Generate clean netlist.

What we are looking for:

Experience: 8–12 years of hands-on RTL Synthesis

EDA exposure: Design compiler, PrimeTime, Tempus, Genus,

Multi-Node Design: Experience working with 16nm, 7nm… etc nodes.